{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:10:44Z","timestamp":1750306244080,"version":"3.41.0"},"reference-count":19,"publisher":"Association for Computing Machinery (ACM)","issue":"3","license":[{"start":{"date-parts":[[2017,5,12]],"date-time":"2017-05-12T00:00:00Z","timestamp":1494547200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["J. Emerg. Technol. Comput. Syst."],"published-print":{"date-parts":[[2017,7,31]]},"abstract":"<jats:p>\n            Neural network (NN) systems are widely used in many important applications ranging from computer vision to speech recognition. To date, most NN systems are processed by general processing units like CPUs or GPUs. However, as the sizes of dataset and network rapidly increase, the original software implementations suffer from long training time. To overcome this problem, specialized hardware accelerators are needed to design high-speed NN systems. This article presents an efficient hardware architecture of restricted Boltzmann machine (RBM) that is an important category of NN systems. Various optimization approaches at the hardware level are performed to improve the training speed.\n            <jats:italic>As-soon-as-possible<\/jats:italic>\n            and\n            <jats:italic>overlapped-scheduling<\/jats:italic>\n            approaches are used to reduce the latency. It is shown that, compared with the flat design, the proposed RBM architecture can achieve 50% reduction in training time. In addition, an\n            <jats:italic>on-the-fly<\/jats:italic>\n            computation scheme is also used to reduce the storage requirement of binary and stochastic states by several hundreds of times. Then, based on the proposed approach, a 784-2252 RBM design example is developed for MNIST handwritten digit recognition dataset. Analysis shows that the VLSI design of RBM achieves significant improvement in training speed and energy efficiency as compared to CPU\/GPU-based solution.\n          <\/jats:p>","DOI":"10.1145\/3007193","type":"journal-article","created":{"date-parts":[[2017,5,15]],"date-time":"2017-05-15T12:13:58Z","timestamp":1494850438000},"page":"1-19","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":4,"title":["VLSI Architectures for the Restricted Boltzmann Machine"],"prefix":"10.1145","volume":"13","author":[{"given":"Bo","family":"Yuan","sequence":"first","affiliation":[{"name":"City University of New York, City College"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6543-2793","authenticated-orcid":false,"given":"Keshab K.","family":"Parhi","sequence":"additional","affiliation":[{"name":"University of Minnesota, Twin Cities"}]}],"member":"320","published-online":{"date-parts":[[2017,5,12]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1049\/ip-cds:19971587"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2010.2078851"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1815993"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/2541940.2541967"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/4.121550"},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2010.5537908"},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1162\/neco.2006.18.7.1527"},{"key":"e_1_2_1_8_1","unstructured":"G. E. Hinton. 2010. A practical guide to training restricted Boltzmann machines. http:\/\/www.cs.toronto.edu\/&sim;hinton\/absps\/guideTR.pdf.  G. E. Hinton. 2010. A practical guide to training restricted Boltzmann machines. http:\/\/www.cs.toronto.edu\/&sim;hinton\/absps\/guideTR.pdf."},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/TIE.2006.888791"},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/2539125"},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2010.38"},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1007\/11760191_192"},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/1508128.1508140"},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/TNN.2003.811357"},{"volume-title":"Proceedings of NIPS 22 Workshop on Deep Learning for Speech Recognition.","author":"Mohamed A. R.","key":"e_1_2_1_15_1","unstructured":"A. R. Mohamed , G. Dahl , and G. E. Hinton . 2009. Deep belief networks for phone recognition . In Proceedings of NIPS 22 Workshop on Deep Learning for Speech Recognition. A. R. Mohamed, G. Dahl, and G. E. Hinton. 2009. Deep belief networks for phone recognition. In Proceedings of NIPS 22 Workshop on Deep Learning for Speech Recognition."},{"volume-title":"VLSI Digital Signal Processing Systems: Design and Implementation","author":"Parhi K. K.","key":"e_1_2_1_16_1","unstructured":"K. K. Parhi . 1999. VLSI Digital Signal Processing Systems: Design and Implementation . Wiley , New York . K. K. Parhi. 1999. VLSI Digital Signal Processing Systems: Design and Implementation. Wiley, New York."},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/12.73588"},{"key":"e_1_2_1_18_1","unstructured":"Y. Teh and G. E. Hinton. 2001. Rate-coded restricted Boltzmann machines for face recognition. In Advances in Neural Information Processing Systems MIT Press Cambridge 908--914.  Y. Teh and G. E. Hinton. 2001. Rate-coded restricted Boltzmann machines for face recognition. In Advances in Neural Information Processing Systems MIT Press Cambridge 908--914."},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-45234-8_120"}],"container-title":["ACM Journal on Emerging Technologies in Computing Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3007193","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3007193","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T04:23:41Z","timestamp":1750220621000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3007193"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,5,12]]},"references-count":19,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2017,7,31]]}},"alternative-id":["10.1145\/3007193"],"URL":"https:\/\/doi.org\/10.1145\/3007193","relation":{},"ISSN":["1550-4832","1550-4840"],"issn-type":[{"type":"print","value":"1550-4832"},{"type":"electronic","value":"1550-4840"}],"subject":[],"published":{"date-parts":[[2017,5,12]]},"assertion":[{"value":"2016-03-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2016-10-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2017-05-12","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}