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Previous works have examined the basics of the following: (1) a computational model that supports the swap-in\/out of a partial datapath\u2014namely, a virtual hardware is realized by hardware, without a host processor and its software; (2) an architecture that has shown a minimum pipeline requirement and a minimum component requirement; and (3) the characteristics of the execution phase and a stack shift that realizes the swap-in\/out. However, these works did not explore the design space, particularly with respect to the following: (1) the clock cycle time on the adaptive processor, which must depend on a wire delay that is primarily used for the global communication of requests, acknowledgments, acquirements, releases, and so forth, and (2) a revised control system that can handle the out-of-order acknowledgment and in-order acquirement that guarantee the correct datapath configuration with a conditional branch for the configurations. This article explores the scaling of the ALU resources versus pipelining of the wires.<\/jats:p>","DOI":"10.1145\/3007902","type":"journal-article","created":{"date-parts":[[2017,4,12]],"date-time":"2017-04-12T12:05:49Z","timestamp":1491998749000},"page":"1-22","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":3,"title":["Performance Scalability of Adaptive Processor Architecture"],"prefix":"10.1145","volume":"10","author":[{"given":"Shigeyuki","family":"Takano","sequence":"first","affiliation":[]}],"member":"320","published-online":{"date-parts":[[2017,4,11]]},"reference":[{"key":"e_1_2_1_1_1","unstructured":"Altera Corp. 2015a. Arria 10 Core Fabric and General Purpose I\/Os Handbook.  Altera Corp. 2015a. Arria 10 Core Fabric and General Purpose I\/Os Handbook."},{"key":"e_1_2_1_2_1","unstructured":"Altera Corp. 2015b. Hyper-Retiming for Stratix 10 Designs.  Altera Corp. 2015b. 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