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Emerg. Technol. Comput. Syst."],"published-print":{"date-parts":[[2017,4,30]]},"abstract":"<jats:p>A one-step sneak-path free read scheme for resistive crossbar memory is proposed in this article. During read operation, it configures the crossbar array into a four-terminal resistance network, which is composed of the selected cell and three other resistors corresponding to unselected cells that contribute to the sneak-path. Two sensing voltages with equal potential are applied to three terminals of the network. One is for sensing the resistance of the selected cell; the other is for creating zero-voltage drop across one of the three resistors, which connects the sneak-path to the selected cell. This effectively suppresses the current injected by the sneak-path to the selected cell-sensing loop. This work also proposes a cost-effective data-encoding circuit that guarantees that at least half of the memory cells are in a high-resistance state, which further minimizes sneak-path current. The impact of key design parameters, such as sensing voltage, switch on-resistance, and the ratio of memory cell resistances in different states, as well as nonideal effects are investigated. Equations for estimating the maximum array size to share a single read circuit are derived. The effectiveness of the proposed design has been validated via circuit simulations. Impacts of the word-\/bit-line resistance are also analyzed.<\/jats:p>","DOI":"10.1145\/3012002","type":"journal-article","created":{"date-parts":[[2017,2,3]],"date-time":"2017-02-03T14:52:35Z","timestamp":1486133555000},"page":"1-18","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":2,"title":["One-Step Sneak-Path Free Read Scheme for Resistive Crossbar Memory"],"prefix":"10.1145","volume":"13","author":[{"given":"Yao","family":"Wang","sequence":"first","affiliation":[{"name":"School of Communication and Information Engineering, University of Electronic Science and Technology of China, Chengdu, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Liang","family":"Rong","sequence":"additional","affiliation":[{"name":"School of Communication and Information Engineering, University of Electronic Science and Technology of China, Chengdu, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Haibo","family":"Wang","sequence":"additional","affiliation":[{"name":"Department of ECE, Southern Illinois University, Carbondale, IL"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Guangjun","family":"Wen","sequence":"additional","affiliation":[{"name":"School of Communication and Information Engineering, University of Electronic Science and Technology of China, Chengdu, China"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2017,2,3]]},"reference":[{"doi-asserted-by":"publisher","key":"e_1_2_1_1_1","DOI":"10.1109\/LED.2010.2082487"},{"doi-asserted-by":"publisher","key":"e_1_2_1_2_1","DOI":"10.1109\/ISIT.2013.6620207"},{"doi-asserted-by":"publisher","key":"e_1_2_1_3_1","DOI":"10.1109\/JSSC.2012.2230515"},{"doi-asserted-by":"publisher","key":"e_1_2_1_4_1","DOI":"10.1109\/VLSI-TSA.2014.6839674"},{"doi-asserted-by":"publisher","key":"e_1_2_1_5_1","DOI":"10.1109\/NANO.2011.6144367"},{"doi-asserted-by":"publisher","key":"e_1_2_1_6_1","DOI":"10.1109\/ISCAS.2012.6271619"},{"doi-asserted-by":"publisher","key":"e_1_2_1_7_1","DOI":"10.1109\/JSSC.2012.2192661"},{"doi-asserted-by":"publisher","key":"e_1_2_1_8_1","DOI":"10.1109\/ISSCC.2011.5746415"},{"doi-asserted-by":"publisher","key":"e_1_2_1_9_1","DOI":"10.1109\/ICMENS.2003.1222018"},{"doi-asserted-by":"publisher","key":"e_1_2_1_10_1","DOI":"10.1109\/ISSCC.2014.6757460"},{"doi-asserted-by":"publisher","key":"e_1_2_1_11_1","DOI":"10.1109\/TED.2012.2211881"},{"doi-asserted-by":"publisher","key":"e_1_2_1_12_1","DOI":"10.1109\/JSSC.2006.888349"},{"doi-asserted-by":"publisher","key":"e_1_2_1_13_1","DOI":"10.1109\/TED.2015.2412960"},{"doi-asserted-by":"publisher","key":"e_1_2_1_14_1","DOI":"10.1109\/ISSCC.2012.6177078"},{"doi-asserted-by":"publisher","key":"e_1_2_1_15_1","DOI":"10.1109\/TVLSI.2013.2256945"},{"doi-asserted-by":"publisher","key":"e_1_2_1_16_1","DOI":"10.1109\/JSSC.2010.2102590"},{"doi-asserted-by":"publisher","key":"e_1_2_1_17_1","DOI":"10.1109\/ISVLSI.2010.32"},{"doi-asserted-by":"publisher","key":"e_1_2_1_18_1","DOI":"10.1145\/2422094.2422103"},{"doi-asserted-by":"publisher","key":"e_1_2_1_19_1","DOI":"10.1109\/ISVLSI.2014.32"},{"doi-asserted-by":"publisher","key":"e_1_2_1_20_1","DOI":"10.1109\/LED.2013.2292938"},{"doi-asserted-by":"publisher","key":"e_1_2_1_21_1","DOI":"10.1109\/TVLSI.2012.2227519"},{"doi-asserted-by":"publisher","key":"e_1_2_1_22_1","DOI":"10.1109\/TCAD.2015.2391254"},{"doi-asserted-by":"publisher","key":"e_1_2_1_23_1","DOI":"10.1109\/TIT.2012.2190380"},{"doi-asserted-by":"publisher","key":"e_1_2_1_24_1","DOI":"10.1109\/ISCAS.2011.5938211"},{"doi-asserted-by":"publisher","key":"e_1_2_1_25_1","DOI":"10.1049\/el.2012.1017"},{"doi-asserted-by":"publisher","key":"e_1_2_1_26_1","DOI":"10.1109\/MWSCAS.2010.5548670"},{"volume-title":"Proceedings of the Symposium on VLSI Technology. 24--25","author":"Sasago Y.","unstructured":"Y. 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