{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,24]],"date-time":"2026-06-24T15:46:00Z","timestamp":1782315960697,"version":"3.54.5"},"reference-count":37,"publisher":"Association for Computing Machinery (ACM)","issue":"3","license":[{"start":{"date-parts":[[2017,4,5]],"date-time":"2017-04-05T00:00:00Z","timestamp":1491350400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","award":["CCF-0917057"],"award-info":[{"award-number":["CCF-0917057"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Des. Autom. Electron. Syst."],"published-print":{"date-parts":[[2017,7,31]]},"abstract":"<jats:p>\n            We propose efficient algorithms to construct a low-power clock tree for through-silicon-via (TSV)-based 3D-ICs. We use shutdown gates to save clock trees\u2019 dynamic power, which selectively turn off certain clock tree branches to avoid unnecessary clock activities when the modules in these tree branches are inactive. While this clock gating technique has been extensively studied in 2D circuits, its application in 3D-ICs is unclear. In 3D-ICs, a shutdown gate is connected to a control signal unit through\n            <jats:italic>control<\/jats:italic>\n            TSVs, which may cause placement conflicts with existing\n            <jats:italic>clock<\/jats:italic>\n            TSVs in the layout due to TSV\u2019s large physical dimension. We develop a two-phase clock tree synthesis design flow for 3D-ICs: (1) 3D abstract clock tree generation based on K-means clustering and (2) clock tree embedding with simultaneous shutdown gates\u2019 insertion based on simulated annealing (SA) and a force-directed TSV placer. Experimental results indicate that (1) the K-means clustering heuristic significantly reduces the clock power by clustering modules with similar switching behavior and close proximity, and (2) the SA algorithm effectively inserts the shutdown gates to a 3D clock tree, while considering\n            <jats:italic>control<\/jats:italic>\n            TSV\u2019s placement. Compared with previous 3D clock tree synthesis techniques, our K-means clustering-based approach achieves larger reduction in clock tree power consumption while ensuring zero clock skew.\n          <\/jats:p>","DOI":"10.1145\/3019610","type":"journal-article","created":{"date-parts":[[2017,4,3]],"date-time":"2017-04-03T12:13:39Z","timestamp":1491221619000},"page":"1-24","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":11,"title":["Low-Power Clock Tree Synthesis for 3D-ICs"],"prefix":"10.1145","volume":"22","author":[{"given":"Tiantao","family":"Lu","sequence":"first","affiliation":[{"name":"University of Maryland, College Park, MD, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Ankur","family":"Srivastava","sequence":"additional","affiliation":[{"name":"University of Maryland, College Park, MD, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2017,4,5]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/323480.323482"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2009.5090684"},{"key":"e_1_2_1_3_1","doi-asserted-by":"crossref","first-page":"11","DOI":"10.1109\/82.204128","article-title":"Zero skew clock routing with minimum wirelength","volume":"39","author":"Chao Ting-Hai","year":"1992","unstructured":"Ting-Hai Chao , Yu-Chin Hsu , Jan-Ming Ho , and A. B. Kahng . 1992 . Zero skew clock routing with minimum wirelength . IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process. 39 , 11 (Nov. 1992), 799--814. Ting-Hai Chao, Yu-Chin Hsu, Jan-Ming Ho, and A. B. Kahng. 1992. Zero skew clock routing with minimum wirelength. IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process. 39, 11 (Nov. 1992), 799--814.","journal-title":"IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process."},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/1297666.1297686"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/775832.775989"},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/157485.165066"},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.924824"},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/177424.178042"},{"key":"e_1_2_1_9_1","unstructured":"ISPD. 2009. Ispd 2009 clock network synthesis contest. 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IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 12, 3 (Mar. 2004), 245--254.","journal-title":"IEEE Trans. Very Large Scale Integr. (VLSI) Syst."},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/2024724.2024900"},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/TIT.1982.1056489"},{"key":"e_1_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2011.2168834"},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/2934583.2934589"},{"key":"e_1_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/2627369.2627665"},{"key":"e_1_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/2742060.2742068"},{"key":"e_1_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2014.2384042"},{"key":"e_1_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2016.7479173"},{"key":"e_1_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2016.69"},{"key":"e_1_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2013.2245375"},{"key":"e_1_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1145\/1383369.1383381"},{"key":"e_1_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.924825"},{"key":"e_1_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2014.2379645"},{"key":"e_1_2_1_29_1","unstructured":"Sematech. 2010. Concerns of 3D Integration Technology Using TSV. Retrieved from http:\/\/www.sematech.org\/ meetings\/archives\/symposia\/9028\/Session2_3D\/Lee_KangWook.pdf.  Sematech. 2010. Concerns of 3D Integration Technology Using TSV. Retrieved from http:\/\/www.sematech.org\/ meetings\/archives\/symposia\/9028\/Session2_3D\/Lee_KangWook.pdf."},{"key":"e_1_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1145\/584091.584093"},{"key":"e_1_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2012.2206592"},{"key":"e_1_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1145\/1735023.1735060"},{"key":"e_1_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2009.2030156"},{"key":"e_1_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.846365"},{"key":"e_1_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1109\/TMSCS.2016.2550460"},{"key":"e_1_2_1_36_1","volume-title":"Proc. 16th Asia South Pac. Des. Autom. Conf. (ASP-DAC\u201911)","author":"Yang Jaeseok","unstructured":"Jaeseok Yang , J. S. Pak , Xin Zhao , Sung Kyu Lim , and D. Z. Pan . 2011. Robust clock tree synthesis with timing yield optimization for 3D-ICs . In Proc. 16th Asia South Pac. Des. Autom. Conf. (ASP-DAC\u201911) . 621--626. Jaeseok Yang, J. S. Pak, Xin Zhao, Sung Kyu Lim, and D. Z. Pan. 2011. Robust clock tree synthesis with timing yield optimization for 3D-ICs. In Proc. 16th Asia South Pac. Des. Autom. Conf. (ASP-DAC\u201911). 621--626."},{"key":"e_1_2_1_37_1","first-page":"2","article-title":"Low-Power and Reliable Clock Network Design for Through-Silicon Via (TSV) Based 3D ICs","volume":"1","author":"Zhao Xin","year":"2011","unstructured":"Xin Zhao , J. Minz , and Sung Kyu Lim . 2011 . Low-Power and Reliable Clock Network Design for Through-Silicon Via (TSV) Based 3D ICs . IEEE Trans. Compon. Packag. Manuf. Technol. 1 , 2 (Feb. 2011), 247--259. Xin Zhao, J. Minz, and Sung Kyu Lim. 2011. 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