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The open-source Verilog-to-Routing (VTR) FPGA architecture evaluation framework [Rose et al. 2012] is extended to generate synthesizable Verilog for its in-memory FPGA architectural device model. The Verilog can subsequently be synthesized into standard cells, placed and routed using an ASIC design flow. A second extension to VTR generates a configuration bitstream for the FPGA, where the bitstream configures the FPGA to realize a user-provided placed and routed design. The proposed framework and methodology makes possible the silicon implementation of a wide range of VTR-modeled FPGA fabrics. In an experimental study, area and timing-optimized FPGA implementations in 65nm TSMC standard cells are compared to a 65nm Altera commercial FPGA. In addition, we consider augmenting the generic standard-cell library from TSMC with a manually designed and laid-out FPGA-specific cell. We demonstrate the utility of the custom cell in reducing the area of the synthesized FPGA fabric.<\/jats:p>","DOI":"10.1145\/3024063","type":"journal-article","created":{"date-parts":[[2017,4,7]],"date-time":"2017-04-07T12:30:24Z","timestamp":1491568224000},"page":"1-23","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":22,"title":["Synthesizable Standard Cell FPGA Fabrics Targetable by the Verilog-to-Routing CAD Flow"],"prefix":"10.1145","volume":"10","author":[{"given":"Jin Hee","family":"Kim","sequence":"first","affiliation":[{"name":"University of Toronto, Ontario, Canada"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Jason H.","family":"Anderson","sequence":"additional","affiliation":[{"name":"University of Toronto, Ontario, Canada"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2017,4,6]]},"reference":[{"key":"e_1_2_1_1_1","volume-title":"Bridging the Gap Between Soft and Hard eFPGA Design. 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