{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,6]],"date-time":"2026-03-06T01:16:47Z","timestamp":1772759807220,"version":"3.50.1"},"reference-count":20,"publisher":"Association for Computing Machinery (ACM)","issue":"2","license":[{"start":{"date-parts":[[2017,3,22]],"date-time":"2017-03-22T00:00:00Z","timestamp":1490140800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Reconfigurable Technol. Syst."],"published-print":{"date-parts":[[2017,6,30]]},"abstract":"<jats:p>We can design an FPGA-optimized lightweight network-on-chip (NoC) router for flit-oriented packet-switched communication that is an order of magnitude smaller (in terms of LUTs and FFs) than state-of-the-art FPGA overlay routers available today. We present Hoplite, an efficient, lightweight, and fast FPGA overlay NoC that is designed to be small and compact by (1) using deflection routing instead of buffered switching to eliminate expensive FIFO buffers and (2) using a torus topology to reduce the cost of switch crossbar. Buffering and crossbar implementation complexities have traditionally limited speeds and imposed heavy resource costs in conventional FPGA overlay NoCs. We take care to exploit the fracturable lookup tables (LUT) organization of the FPGA to further improve the resource efficiency of mapping the expensive crossbar multiplexers. Hoplite can outperform classic, bidirectional, buffered mesh networks for single-flit-oriented FPGA applications by as much as 1.5 \u00d7 (best achievable throughputs for a 10 \u00d7 10 system) or 2.5 \u00d7 (allocating same amount of FPGA resources to both NoCs) for uniform random traffic. When compared to buffered mesh switches, FPGA-based deflection routers are \u2248 3.5 \u00d7 smaller (HLS-generated switch) and 2.5 \u00d7 faster (clock period) for 32b payloads. In a separate experiment, we hand-crafted an RTL version of our switch with location constraints that requires only 60 LUTs and 100 FFs per router and runs at 2.9ns. We conduct additional layout experiments on modern Xilinx and Altera FPGAs and demonstrate wide-channel chip-spanning layouts that run in excess of 300MHz while consuming 10--15% of overall chip resources. We also demonstrate a clustered RISC-V multiprocessor organization that uses Hoplite to help deliver the high processing throughputs of the FPGA architecture to user applications.<\/jats:p>","DOI":"10.1145\/3027486","type":"journal-article","created":{"date-parts":[[2017,3,23]],"date-time":"2017-03-23T16:19:44Z","timestamp":1490285984000},"page":"1-24","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":35,"title":["Hoplite"],"prefix":"10.1145","volume":"10","author":[{"given":"Nachiket","family":"Kapre","sequence":"first","affiliation":[{"name":"University of Waterloo, Waterloo, Canada"}]},{"given":"Jan","family":"Gray","sequence":"additional","affiliation":[{"name":"Gray Research LLC, Bellevue, USA"}]}],"member":"320","published-online":{"date-parts":[[2017,3,22]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2012.19"},{"key":"e_1_2_1_2_1","volume-title":"Proceedings of the 2012 International Conference on Field-Programmable Technology (FPT). 95--103","author":"Abdelfattah M. S.","unstructured":"M. S. Abdelfattah and V. Betz . 2012. Design tradeoffs for hard and soft FPGA-based networks-on-chip . In Proceedings of the 2012 International Conference on Field-Programmable Technology (FPT). 95--103 . M. S. Abdelfattah and V. Betz. 2012. Design tradeoffs for hard and soft FPGA-based networks-on-chip. In Proceedings of the 2012 International Conference on Field-Programmable Technology (FPT). 95--103."},{"key":"e_1_2_1_3_1","volume-title":"Applying the Benefits of Network on a Chip Architecture to FPGA System Design. Altera White Paper. (Apr","year":"2011","unstructured":"Altera. 2011. Applying the Benefits of Network on a Chip Architecture to FPGA System Design. Altera White Paper. (Apr . 2011 ). Retrieved from https:\/\/www.altera.com\/en_US\/pdfs\/literature\/wp\/wp-01149-noc-qsys.pdf. Altera. 2011. Applying the Benefits of Network on a Chip Architecture to FPGA System Design. Altera White Paper. (Apr. 2011). Retrieved from https:\/\/www.altera.com\/en_US\/pdfs\/literature\/wp\/wp-01149-noc-qsys.pdf."},{"key":"e_1_2_1_4_1","volume-title":"Arria 10 Core Fabric and General Purpose I\/Os Handbook. Retrieved","author":"Altera Corp. 2015.","year":"2015","unstructured":"Altera Corp. 2015. Arria 10 Core Fabric and General Purpose I\/Os Handbook. Retrieved May 2015 from https:\/\/www.altera.com\/en_US\/pdfs\/literature\/hb\/arria-10\/a10_handbook.pdf. Altera Corp. 2015. Arria 10 Core Fabric and General Purpose I\/Os Handbook. Retrieved May 2015 from https:\/\/www.altera.com\/en_US\/pdfs\/literature\/hb\/arria-10\/a10_handbook.pdf."},{"key":"e_1_2_1_6_1","first-page":"802","article-title":"Comments on CSMA","volume":"802","year":"1992","unstructured":"Buchholz. 1992 . Comments on CSMA . IEEE 802 , 11 (1992), 802 -- 811 . Buchholz. 1992. Comments on CSMA. IEEE 802, 11 (1992), 802--11.","journal-title":"IEEE"},{"key":"e_1_2_1_7_1","volume-title":"Proceedings of the 16th International Symposium on Quality Electronic Design. 475--484","author":"Cai Y.","unstructured":"Y. Cai , K. Mai , and O. Mutlu . 2015. Comparative evaluation of FPGA and ASIC implementations of bufferless and buffered routing algorithms for on-chip networks . In Proceedings of the 16th International Symposium on Quality Electronic Design. 475--484 . Y. Cai, K. Mai, and O. Mutlu. 2015. Comparative evaluation of FPGA and ASIC implementations of bufferless and buffered routing algorithms for on-chip networks. In Proceedings of the 16th International Symposium on Quality Electronic Design. 475--484."},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/378239.379048"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2012.8"},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/ReConFig.2014.7032481"},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2016.12"},{"key":"e_1_2_1_12_1","volume-title":"Proceedings of the 2012 International Conference on Field-Programmable Technology (FPT). 47--52","author":"Huan Yutian","unstructured":"Yutian Huan and A. DeHon . 2012. FPGA optimized packet-switched NoC using split and merge primitives . In Proceedings of the 2012 International Conference on Field-Programmable Technology (FPT). 47--52 . Yutian Huan and A. DeHon. 2012. FPGA optimized packet-switched NoC using split and merge primitives. In Proceedings of the 2012 International Conference on Field-Programmable Technology (FPT). 47--52."},{"key":"e_1_2_1_13_1","volume-title":"Understanding How the New HyperFlex Architecture Enables Next-Generation High-Performance Systems. Altera White Paper. Retrieved","author":"Hutton Mike","year":"2015","unstructured":"Mike Hutton . 2015. Understanding How the New HyperFlex Architecture Enables Next-Generation High-Performance Systems. Altera White Paper. Retrieved April 2015 from https:\/\/www.altera.com\/content\/dam\/altera-www\/global\/en_US\/pdfs\/literature\/wp\/wp-01231-understanding-how-hyperflex-architecture-enables-high-performance-systems.pdf. Mike Hutton. 2015. Understanding How the New HyperFlex Architecture Enables Next-Generation High-Performance Systems. Altera White Paper. Retrieved April 2015 from https:\/\/www.altera.com\/content\/dam\/altera-www\/global\/en_US\/pdfs\/literature\/wp\/wp-01231-understanding-how-hyperflex-architecture-enables-high-performance-systems.pdf."},{"key":"e_1_2_1_14_1","volume-title":"Proceedings of the 2015 25th International Conference on Field Programmable Logic and Applications (FPL). 1--8.","author":"Kapre N.","unstructured":"N. Kapre and J. Gray . 2015. Hoplite: Building austere overlay NoCs for FPGAs . In Proceedings of the 2015 25th International Conference on Field Programmable Logic and Applications (FPL). 1--8. N. Kapre and J. Gray. 2015. Hoplite: Building austere overlay NoCs for FPGAs. In Proceedings of the 2015 25th International Conference on Field Programmable Logic and Applications (FPL). 1--8."},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2006.55"},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669145"},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/T-C.1971.223159"},{"key":"e_1_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2010.10"},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/1555815.1555781"},{"key":"e_1_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/2145694.2145703"},{"key":"e_1_2_1_21_1","volume-title":"7 Series FPGAs Configurable Logic Block User Guide. Retrieved","author":"Xilinx Inc. 2015.","year":"2015","unstructured":"Xilinx Inc. 2015. 7 Series FPGAs Configurable Logic Block User Guide. Retrieved February 2015 from http:\/\/www.xilinx.com\/support\/documentation\/user_guides\/ug474_7Series_CLB .pdf. Xilinx Inc. 2015. 7 Series FPGAs Configurable Logic Block User Guide. Retrieved February 2015 from http:\/\/www.xilinx.com\/support\/documentation\/user_guides\/ug474_7Series_CLB .pdf."}],"container-title":["ACM Transactions on Reconfigurable Technology and Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3027486","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3027486","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T04:24:01Z","timestamp":1750220641000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3027486"}},"subtitle":["A Deflection-Routed Directional Torus NoC for FPGAs"],"short-title":[],"issued":{"date-parts":[[2017,3,22]]},"references-count":20,"journal-issue":{"issue":"2","published-print":{"date-parts":[[2017,6,30]]}},"alternative-id":["10.1145\/3027486"],"URL":"https:\/\/doi.org\/10.1145\/3027486","relation":{},"ISSN":["1936-7406","1936-7414"],"issn-type":[{"value":"1936-7406","type":"print"},{"value":"1936-7414","type":"electronic"}],"subject":[],"published":{"date-parts":[[2017,3,22]]},"assertion":[{"value":"2016-04-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2016-12-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2017-03-22","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}