{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:08:34Z","timestamp":1750306114653,"version":"3.41.0"},"reference-count":11,"publisher":"Association for Computing Machinery (ACM)","issue":"4","license":[{"start":{"date-parts":[[2017,1,11]],"date-time":"2017-01-11T00:00:00Z","timestamp":1484092800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["SIGARCH Comput. Archit. News"],"published-print":{"date-parts":[[2017,1,11]]},"abstract":"<jats:p>Designing with Hardware Description Languages (HDLs) is still the de facto standard way to develop FPGA-based custom computing systems, and RTL simulation is an important step in ensuring that the designed hardware behavior meets the design specification. In this paper, we propose a new high-speed Verilog HDL simulation method. It is based on two previously proposed techniques: ArchHDL and Pyverilog. ArchHDL is used as a simulation engine in the method because the RTL simulation provided by ArchHDL can be parallelized with OpenMP. We use Pyverilog to develop a code translator to convert Verilog HDL source code into ArchHDL code, and due to this, the translator can be realized and its implementation is lightweight. We compare the proposed method with Synopsys VCS, and the experimental results show that the RTL simulation behavior and speed are same as that of Synopsys VCS and up to 5.8x better respectively.<\/jats:p>","DOI":"10.1145\/3039902.3039908","type":"journal-article","created":{"date-parts":[[2017,1,17]],"date-time":"2017-01-17T13:42:08Z","timestamp":1484660528000},"page":"26-31","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":1,"title":["A High-speed Verilog HDL Simulation Method using a Lightweight Translator"],"prefix":"10.1145","volume":"44","author":[{"given":"Ryohei","family":"Kobayashi","sequence":"first","affiliation":[{"name":"University of Tsukuba, Japan"}]},{"given":"Tomohiro","family":"Misono","sequence":"additional","affiliation":[{"name":"Tokyo Institute of Technology, Japan"}]},{"given":"Kenji","family":"Kise","sequence":"additional","affiliation":[{"name":"Tokyo Institute of Technology, Japan"}]}],"member":"320","published-online":{"date-parts":[[2017,1,11]]},"reference":[{"key":"e_1_2_1_1_1","unstructured":"Large FPGA Methodology Guide. http:\/\/www.xilinx.com\/support\/documentation\/swmanuals\/xilinx147\/ug872largefpga.pdf.  Large FPGA Methodology Guide. http:\/\/www.xilinx.com\/support\/documentation\/swmanuals\/xilinx147\/ug872largefpga.pdf."},{"key":"e_1_2_1_2_1","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"crossref","first-page":"53","DOI":"10.1007\/978-3-319-16214-0_5","volume-title":"Applied Reconfigurable Computing","author":"Sato Shimpei","year":"2015","unstructured":"Shimpei Sato and Kenji Kise . Archhdl: A novel hardware rtl design environment in c++ . In Kentaro Sano, Dimitrios Soudris, Michael Hubner, and Pedro C. Diniz, editors, Applied Reconfigurable Computing , volume 9040 of Lecture Notes in Computer Science , pages 53 -- 64 . Springer International Publishing , 2015 . Shimpei Sato and Kenji Kise. Archhdl: A novel hardware rtl design environment in c++. In Kentaro Sano, Dimitrios Soudris, Michael Hubner, and Pedro C. Diniz, editors, Applied Reconfigurable Computing, volume 9040 of Lecture Notes in Computer Science, pages 53--64. Springer International Publishing, 2015."},{"key":"e_1_2_1_3_1","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"crossref","first-page":"451","DOI":"10.1007\/978-3-319-16214-0_42","volume-title":"Applied Reconfigurable Computing","author":"Takamaeda-Yamazaki Shinya","year":"2015","unstructured":"Shinya Takamaeda-Yamazaki . Pyverilog: A python-based hardware design processing toolkit for verilog hdl . In Kentaro Sano, Dimitrios Soudris, Michael Hubner, and Pedro C. Diniz, editors, Applied Reconfigurable Computing , volume 9040 of Lecture Notes in Computer Science , pages 451 -- 460 . Springer International Publishing , 2015 . Shinya Takamaeda-Yamazaki. Pyverilog: A python-based hardware design processing toolkit for verilog hdl. In Kentaro Sano, Dimitrios Soudris, Michael Hubner, and Pedro C. Diniz, editors, Applied Reconfigurable Computing, volume 9040 of Lecture Notes in Computer Science, pages 451--460. Springer International Publishing, 2015."},{"key":"e_1_2_1_4_1","unstructured":"Synopsys vcs. http:\/\/www.synopsys.com\/products\/simulation\/simulation.html.  Synopsys vcs. http:\/\/www.synopsys.com\/products\/simulation\/simulation.html."},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.5555\/1899721.1899753"},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228382"},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.5555\/2132325.2132477"},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.18637\/jss.v008.i14"},{"key":"e_1_2_1_9_1","unstructured":"Icarus verilog. http:\/\/iverilog.icarus.com\/.  Icarus verilog. http:\/\/iverilog.icarus.com\/."},{"key":"e_1_2_1_10_1","unstructured":"Ply (python lex-yacc). http:\/\/www.dabeaz.com\/ply\/.  Ply (python lex-yacc). http:\/\/www.dabeaz.com\/ply\/."},{"key":"e_1_2_1_11_1","unstructured":"Jinja. http:\/\/jinja.pocoo.org\/.  Jinja. http:\/\/jinja.pocoo.org\/."}],"container-title":["ACM SIGARCH Computer Architecture News"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3039902.3039908","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3039902.3039908","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T03:36:31Z","timestamp":1750217791000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3039902.3039908"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,1,11]]},"references-count":11,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2017,1,11]]}},"alternative-id":["10.1145\/3039902.3039908"],"URL":"https:\/\/doi.org\/10.1145\/3039902.3039908","relation":{},"ISSN":["0163-5964"],"issn-type":[{"type":"print","value":"0163-5964"}],"subject":[],"published":{"date-parts":[[2017,1,11]]},"assertion":[{"value":"2017-01-11","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}