{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:08:35Z","timestamp":1750306115125,"version":"3.41.0"},"reference-count":15,"publisher":"Association for Computing Machinery (ACM)","issue":"4","license":[{"start":{"date-parts":[[2017,1,11]],"date-time":"2017-01-11T00:00:00Z","timestamp":1484092800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["SIGARCH Comput. Archit. News"],"published-print":{"date-parts":[[2017,1,11]]},"abstract":"<jats:p>In this paper we present a high density three-dimensional (3D) interconnect network implementation based on a modified Mesh-of-Trees (MoT) topology for an embedded FPGA architecture design targeted for high performance 3D integration. To obtain the optimal MoT-based interconnect structure, the routing architecture of the 2D MoT-based FPGA is modified to include long routing segments that span multiple switch blocks in every row and column. By adjusting the percentage of long wire and span, a 2.5D or 3D high density MoT-based embedded FPGAs can be designed. For the 3D multi-stacked MoT-based FPGAs, the 2D MoTbased FPGA is sliced into two or more equal sections by adjusting the length of the long wire span. The long wire segments are realized using 3D through silicon via (TSVs) and 2.5D interposer-based multi-FPGAs, we increase the number of cuts and apply appropriate optimization models to scale down the number of long wires and horizontal inter-FPGA interposer wires. Using our 2.5\/3D CAD models, we demonstrate the speed and area of 3D MoT-based FPGA architecture improved by 54% and 41% respectively in comparison to 3D Mesh-based FPGAs.<\/jats:p>","DOI":"10.1145\/3039902.3039912","type":"journal-article","created":{"date-parts":[[2017,1,17]],"date-time":"2017-01-17T13:42:08Z","timestamp":1484660528000},"page":"50-55","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["Novel Three-Dimensional Embedded FPGA Technology and Achitecture"],"prefix":"10.1145","volume":"44","author":[{"given":"Vinod","family":"Pangracious","sequence":"first","affiliation":[{"name":"American University in Dubai, Dubai, UAE"}]},{"given":"Mulhim","family":"Al-Doori","sequence":"additional","affiliation":[{"name":"American University in Dubai, Dubai, UAE"}]}],"member":"320","published-online":{"date-parts":[[2017,1,11]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2005.150"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/ReConFig.2013.6732282"},{"key":"e_1_2_1_3_1","first-page":"206","volume-title":"ACM Symposium on Parallel Algorithms and Architectures series","author":"Betz V.","year":"2000","unstructured":"V. Betz , A. Marquardt , and J. Rose . Architecture and cad for deep-submicron FPGA . ACM Symposium on Parallel Algorithms and Architectures series , pages 206 -- 215 , 2000 . V. Betz, A. Marquardt, and J. Rose. Architecture and cad for deep-submicron FPGA. ACM Symposium on Parallel Algorithms and Architectures series, pages 206--215, 2000."},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2004.834237"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2004.834237"},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/1216919.1216923"},{"key":"e_1_2_1_7_1","unstructured":"X. Inc. Vertex 5: Multi-platform FPGA. www.xilinx.com.  X. Inc. Vertex 5: Multi-platform FPGA. www.xilinx.com."},{"key":"e_1_2_1_8_1","doi-asserted-by":"crossref","DOI":"10.1007\/978-1-4757-4941-0","volume-title":"Design of interconnect networks for programmable logic","author":"Lemieux G.","year":"2004","unstructured":"G. Lemieux and D. Lewis . Design of interconnect networks for programmable logic . Kluwer Academic Publications , Dordrecht The Netherlands, 2004 . G. Lemieux and D. Lewis. Design of interconnect networks for programmable logic. Kluwer Academic Publications, Dordrecht The Netherlands, 2004."},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/611817.611821"},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/1117201.1117219"},{"key":"e_1_2_1_11_1","volume-title":"Designing a 3d tree-based fpga: Optimization of butterfly programmable interconnect topology using 3d technology","author":"Pangracious V.","year":"2013","unstructured":"V. Pangracious , Z. Marrakchi , and H. Mehrez . Designing a 3d tree-based fpga: Optimization of butterfly programmable interconnect topology using 3d technology . IEEE 3DIC Conferenece- 2013 , 2003. V. Pangracious, Z. Marrakchi, and H. Mehrez. Designing a 3d tree-based fpga: Optimization of butterfly programmable interconnect topology using 3d technology. IEEE 3DIC Conferenece-2013, 2003."},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-36812-7_19"},{"key":"e_1_2_1_13_1","first-page":"1217","volume-title":"Architecture of programmable gate arrays: The effect of logic block functionality on area efficiency","author":"Rose J.","year":"1990","unstructured":"J. Rose , R.J. Francis , D. Lewis , and P. Chow . Architecture of programmable gate arrays: The effect of logic block functionality on area efficiency . IEEE journal of Solid State Circuits , pages 1217 -- 1225 , 1990 . J. Rose, R.J. Francis, D. Lewis, and P. Chow. Architecture of programmable gate arrays: The effect of logic block functionality on area efficiency. IEEE journal of Solid State Circuits, pages 1217--1225, 1990."},{"key":"e_1_2_1_14_1","first-page":"08","article-title":"Architecture level exploration of alternative schmes targeting 3D FPGAs: A software supported methodology","author":"Siozios K.","year":"2008","unstructured":"K. Siozios , A. Bartzas , and D. Soudris . Architecture level exploration of alternative schmes targeting 3D FPGAs: A software supported methodology . Inter. J. of Reconfigurable Computing , 08 , 2008 . K. Siozios, A. Bartzas, and D. Soudris. Architecture level exploration of alternative schmes targeting 3D FPGAs: A software supported methodology. Inter. J. of Reconfigurable Computing, 08, 2008.","journal-title":"Inter. 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