{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,25]],"date-time":"2026-04-25T08:43:55Z","timestamp":1777106635662,"version":"3.51.4"},"reference-count":26,"publisher":"Association for Computing Machinery (ACM)","issue":"4","license":[{"start":{"date-parts":[[2017,1,11]],"date-time":"2017-01-11T00:00:00Z","timestamp":1484092800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["SIGARCH Comput. Archit. News"],"published-print":{"date-parts":[[2017,1,11]]},"abstract":"<jats:p>Computing performance and scalability are the essential basics in modern data centres. Field Programmable Gate Arrays (FPGAs) provide a promising opportunity to improve performance, security and energy efficiency. Especially background acceleration of computationally complex and long-running tasks is an important field of application. A flexible use of reconfigurable devices within a cloud context requires an abstraction of the actual hardware through virtualization.<\/jats:p>\n          <jats:p>In this paper we present an approach inspired by paravirtualized machines for the integration of reconfigurable hardware into cloud services. Using partial reconfiguration our hardware and software framework virtualizes a single physical FPGA to enable multiple independent user designs. Essential components are the management of those virtual user-defined accelerators (vFPGA) and their migration between physical FPGAs to achieve higher system-wide utilization. The migration requires saving and restoring the internal state or context of the vFPGA. We demonstrate the application possibilities and the resource trade-off of our approach by transferring a running design from one physical FPGA to another. Moreover, we present future perspectives for the use of FPGAs in cloud-based environments.<\/jats:p>","DOI":"10.1145\/3039902.3039913","type":"journal-article","created":{"date-parts":[[2017,1,17]],"date-time":"2017-01-17T13:42:08Z","timestamp":1484660528000},"page":"56-61","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":17,"title":["Migration of long-running Tasks between Reconfigurable Resources using Virtualization"],"prefix":"10.1145","volume":"44","author":[{"given":"Oliver","family":"Knodel","sequence":"first","affiliation":[{"name":"Technische Universit\u00e4t Dresden, Dresden, Germany"}]},{"given":"Paul R.","family":"Genssler","sequence":"additional","affiliation":[{"name":"Technische Universit\u00e4t Dresden, Dresden, Germany"}]},{"given":"Rainer G.","family":"Spallek","sequence":"additional","affiliation":[{"name":"Technische Universit\u00e4t Dresden, Dresden, Germany"}]}],"member":"320","published-online":{"date-parts":[[2017,1,11]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.6028\/NIST.SP.800-145"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/1721654.1721672"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/ASAP.2011.6043268"},{"key":"e_1_2_1_4_1","volume-title":"in Communications, Computers and Signal Processing","author":"Mondol J.-A.","year":"2011","unstructured":"J.-A. Mondol , \"Cloud security solutions using FPGA\" , in Communications, Computers and Signal Processing , IEEE , 2011 . J.-A. Mondol, \"Cloud security solutions using FPGA\", in Communications, Computers and Signal Processing, IEEE, 2011."},{"key":"e_1_2_1_5_1","volume-title":"IEEE","author":"Putnam A.","year":"2014","unstructured":"A. Putnam reconfigurable fabric for accelerating large-scale datacenter services\", in Computer Architecture (ISCA), 41st Int'l Symp. on , IEEE , 2014 . A. Putnam et al., \"A reconfigurable fabric for accelerating large-scale datacenter services\", in Computer Architecture (ISCA), 41st Int'l Symp. on, IEEE, 2014."},{"key":"e_1_2_1_6_1","volume-title":"Parallel and Distributed Processing","author":"Fornaciari W.","year":"1998","unstructured":"W. Fornaciari and V. Piuri , \" Virtual FPGAs: Some steps behind the physical barriers \", in Parallel and Distributed Processing , Springer , 1998 . W. Fornaciari and V. Piuri, \"Virtual FPGAs: Some steps behind the physical barriers\", in Parallel and Distributed Processing, Springer, 1998."},{"key":"e_1_2_1_7_1","unstructured":"Xilinx Inc. \"Partial Reconfiguration - User Guide (UG702 v14.5)\" April 26 2013.  Xilinx Inc. \"Partial Reconfiguration - User Guide (UG702 v14.5)\" April 26 2013."},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2012.6339242"},{"key":"e_1_2_1_9_1","volume-title":"Cloud and Big Data Computing, Int'l Conf. on, IEEE","author":"Weerasinghe J.","year":"2015","unstructured":"J. Weerasinghe \"Enabling FPGAs in Hyperscale Data Centers \" , in Cloud and Big Data Computing, Int'l Conf. on, IEEE , 2015 . J. Weerasinghe et al., \"Enabling FPGAs in Hyperscale Data Centers\", in Cloud and Big Data Computing, Int'l Conf. on, IEEE, 2015."},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/2145694.2145728"},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/1331331.1331338"},{"key":"e_1_2_1_12_1","volume-title":"Hardware\/Software Codesign and System Synthesis, Int'l Conf. on","author":"Wang W.","year":"2013","unstructured":"W. Wang , \" pvFPGA: Accessing an FPGA-based hardware accelerator in a paravirtualized environment .\", Hardware\/Software Codesign and System Synthesis, Int'l Conf. on , 2013 . W. Wang et al., \"pvFPGA: Accessing an FPGA-based hardware accelerator in a paravirtualized environment.\", Hardware\/Software Codesign and System Synthesis, Int'l Conf. on, 2013."},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/2597917.2597929"},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/.40"},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2010.76"},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-36812-7_18"},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-16214-0_7"},{"key":"e_1_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/1216919.1216950"},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1109\/AHS.2007.4"},{"key":"e_1_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/CloudCom.2015.60"},{"key":"e_1_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1109\/MC.1974.6323581"},{"key":"e_1_2_1_22_1","volume-title":"Virtual machines: versatile platforms for systems and processes","author":"Smith J.","year":"2005","unstructured":"J. Smith and R. Nair , Virtual machines: versatile platforms for systems and processes . Elsevier , 2005 . J. Smith and R. Nair, Virtual machines: versatile platforms for systems and processes. Elsevier, 2005."},{"key":"e_1_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1145\/1016998.1017000"},{"key":"e_1_2_1_24_1","volume-title":"FPGAs for Software Programmers (FSP), Second Int'l Workshop on","author":"Knodel O.","year":"2015","unstructured":"O. Knodel , \" RC3E: Provision and Management of Reconfigurable Hardware Accelerators in a Cloud Environment \", FPGAs for Software Programmers (FSP), Second Int'l Workshop on , 2015 . O. Knodel et al., \"RC3E: Provision and Management of Reconfigurable Hardware Accelerators in a Cloud Environment\", FPGAs for Software Programmers (FSP), Second Int'l Workshop on, 2015."},{"key":"e_1_2_1_25_1","unstructured":"Xilinx Inc. \"Virtex-II Platform FPGA -- User Guide (UG002 v1.0)\" June 12 2000.  Xilinx Inc. \"Virtex-II Platform FPGA -- User Guide (UG002 v1.0)\" June 12 2000."},{"key":"e_1_2_1_26_1","volume-title":"IEEE","author":"Backasch R.","year":"2014","unstructured":"R. Backasch homogenous reconfigurable regions in heterogeneous FPGAs for module relocation\", in ReConFigurable Computing and FPGAs (ReConFig), Int'l Conf. on , IEEE , 2014 . R. Backasch et al., \"Identifying homogenous reconfigurable regions in heterogeneous FPGAs for module relocation\", in ReConFigurable Computing and FPGAs (ReConFig), Int'l Conf. on, IEEE, 2014."}],"container-title":["ACM SIGARCH Computer Architecture News"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3039902.3039913","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3039902.3039913","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T03:36:31Z","timestamp":1750217791000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3039902.3039913"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,1,11]]},"references-count":26,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2017,1,11]]}},"alternative-id":["10.1145\/3039902.3039913"],"URL":"https:\/\/doi.org\/10.1145\/3039902.3039913","relation":{},"ISSN":["0163-5964"],"issn-type":[{"value":"0163-5964","type":"print"}],"subject":[],"published":{"date-parts":[[2017,1,11]]},"assertion":[{"value":"2017-01-11","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}