{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:08:34Z","timestamp":1750306114471,"version":"3.41.0"},"reference-count":17,"publisher":"Association for Computing Machinery (ACM)","issue":"4","license":[{"start":{"date-parts":[[2017,1,11]],"date-time":"2017-01-11T00:00:00Z","timestamp":1484092800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["SIGARCH Comput. Archit. News"],"published-print":{"date-parts":[[2017,1,11]]},"abstract":"<jats:p>Three-dimensional stacked integrated circuits (3D-SICs) have been expected to overcome the limitations of conventional two-dimensional (2-D) implemented circuits. Since a stacking strategy affects the performance and the power consumption of 3D-SICs, this paper examines two stacking strategies for designing the 3-D stacked floating-point fused multiplyadd (FP-FMA) module which contains four FP-FMA units. Experimental results show that a coarse-grain stacking strategy is suitable for reducing critical path delay of the 3-D stacked FP-FMA module. On the other hand, a fine-grain stacking strategy is suitable for reducing power consumption. The 3-D stacked FP-FMA module which is designed based on a fine-grain stacking strategy achieves an 8.4% critical path delay reduction and an 18% average power reduction compared with the 2-D implementation.<\/jats:p>","DOI":"10.1145\/3039902.3039914","type":"journal-article","created":{"date-parts":[[2017,1,17]],"date-time":"2017-01-17T13:42:08Z","timestamp":1484660528000},"page":"62-67","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":1,"title":["Effects of Stacking Granularity on 3-D Stacked Floating-point Fused Multiply Add Units"],"prefix":"10.1145","volume":"44","author":[{"given":"Jubee","family":"Tada","sequence":"first","affiliation":[{"name":"Yamagata University, Yamagata, Japan"}]},{"given":"Maiki","family":"Hosokawa","sequence":"additional","affiliation":[{"name":"Yamagata University, Yamagata, Japan"}]},{"given":"Ryusuke","family":"Egawa","sequence":"additional","affiliation":[{"name":"Tohoku University, Miyagi, Japan"}]},{"given":"Hiroaki","family":"Kobayashi","sequence":"additional","affiliation":[{"name":"Tohoku University, Miyagi, Japan"}]}],"member":"320","published-online":{"date-parts":[[2017,1,11]]},"reference":[{"key":"e_1_2_1_1_1","first-page":"98","volume-title":"3rd IEEE International Design and Test Workshop","author":"Haron Z.B.","year":"2008","unstructured":"N. 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Kim, \"Electrical Performance of High Bandwidth Memory (HBM) Interposer Channel in Terabyte\/s Bandwidth Graphics Module,\" Proc. IEEE International Conf. on 3D System Integration, Aug. 2015, no. II-2."},{"key":"e_1_2_1_5_1","volume-title":"IEEE International Conf. on 3D System Integration","author":"Goto M.","year":"2015","unstructured":"M. Goto , K. Hagiwara , Y. Iguchi , H. Ohtake , T. Saraya , M. Kobayashi , E. Higurashi , H. Toshiyoshi , and T. Hiramoto , \" Three-dimensional Integrated Circuits and Stacked CMOS Image Sensors Using Direct Bonding of SOI Layers,\" Proc . IEEE International Conf. on 3D System Integration , Aug. 2015 , no. IX-2. M. Goto, K. Hagiwara, Y. Iguchi, H. Ohtake, T. Saraya, M. Kobayashi, E. Higurashi, H. Toshiyoshi, and T. Hiramoto, \"Three-dimensional Integrated Circuits and Stacked CMOS Image Sensors Using Direct Bonding of SOI Layers,\" Proc. IEEE International Conf. on 3D System Integration, Aug. 2015, no. IX-2."},{"key":"e_1_2_1_6_1","volume-title":"IEEE International Conf. on 3D System Integration 2011","author":"Tada J.","year":"2012","unstructured":"J. Tada , R. Egawa , K. Kawai , H. Kobayashi , and G. Goto , \" A middle-grain circuit partitioning strategy for 3-D integrated floating-point multipliers,\" Proc . IEEE International Conf. on 3D System Integration 2011 , Jan. 2012 , no. P-2-21. J. Tada, R. Egawa, K. Kawai, H. Kobayashi, and G. Goto, \"A middle-grain circuit partitioning strategy for 3-D integrated floating-point multipliers,\" Proc. IEEE International Conf. on 3D System Integration 2011, Jan. 2012, no. P-2-21."},{"key":"e_1_2_1_7_1","volume-title":"IEEE International Conf. on 3D System Integration 2013","author":"Tada J.","year":"2013","unstructured":"J. Tada , R. Egawa , and H. Kobayashi , \" Design of a 3-D Stacked Floating- Point Adder,\" Proc . IEEE International Conf. on 3D System Integration 2013 , Oct. 2013 . J. Tada, R. Egawa, and H. Kobayashi, \"Design of a 3-D Stacked Floating- Point Adder,\" Proc. IEEE International Conf. on 3D System Integration 2013, Oct. 2013."},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.5555\/2133429.2133571"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/VLSI.Design.2010.60"},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/VLSID.2007.41"},{"key":"e_1_2_1_11_1","volume-title":"Arithmetic unit design using 180 nm TSV-based 3d stacking technology,\" Proc","author":"Ouyang J.","year":"2009","unstructured":"J. Ouyang , G. Sun , Y. Chen , L. Duan , T. Zhang , Y. Xie , and M. J. Irwin , \" Arithmetic unit design using 180 nm TSV-based 3d stacking technology,\" Proc . IEEE International 3D System Integration Conf . 2009 , Sept. 2009. J. Ouyang, G. Sun, Y. Chen, L. Duan, T. Zhang, Y. Xie, and M. J. Irwin, \"Arithmetic unit design using 180 nm TSV-based 3d stacking technology,\" Proc. IEEE International 3D System Integration Conf. 2009, Sept. 2009."},{"key":"e_1_2_1_12_1","volume-title":"Evaluation of fine grain 3D integrated arithmetic units,\" Proc","author":"Egawa R.","year":"2009","unstructured":"R. Egawa , J. Tada , H. Kobayashi , and G. Goto , \" Evaluation of fine grain 3D integrated arithmetic units,\" Proc . IEEE International 3D System Integration Conf . 2009 , Sept. 2009. R. Egawa, J. Tada, H. Kobayashi, and G. Goto, \"Evaluation of fine grain 3D integrated arithmetic units,\" Proc. IEEE International 3D System Integration Conf. 2009, Sept. 2009."},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/1278480.1278636"},{"key":"e_1_2_1_14_1","volume-title":"IEEE International Conf. on 3D System Integration 2014","author":"Franzon P. D.","year":"2014","unstructured":"P. D. Franzon , E. Rotenberg , J. Tuck , H. Zhou , W. R. Davis , H. Dai , J. Huh , S. Ku , S. Lipa , C. Li , J. B. Park , and J. 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IEEE International Conf. on 3D System Integration 2014, Dec. 2014."},{"key":"e_1_2_1_17_1","unstructured":"The International Technology Roadmap for Semiconductors 2010 Update http:\/\/www.itrs.net\/  The International Technology Roadmap for Semiconductors 2010 Update http:\/\/www.itrs.net\/"}],"container-title":["ACM SIGARCH Computer Architecture News"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3039902.3039914","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3039902.3039914","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T03:36:31Z","timestamp":1750217791000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3039902.3039914"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,1,11]]},"references-count":17,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2017,1,11]]}},"alternative-id":["10.1145\/3039902.3039914"],"URL":"https:\/\/doi.org\/10.1145\/3039902.3039914","relation":{},"ISSN":["0163-5964"],"issn-type":[{"type":"print","value":"0163-5964"}],"subject":[],"published":{"date-parts":[[2017,1,11]]},"assertion":[{"value":"2017-01-11","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}