{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:08:35Z","timestamp":1750306115233,"version":"3.41.0"},"reference-count":13,"publisher":"Association for Computing Machinery (ACM)","issue":"4","license":[{"start":{"date-parts":[[2017,1,11]],"date-time":"2017-01-11T00:00:00Z","timestamp":1484092800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["SIGARCH Comput. Archit. News"],"published-print":{"date-parts":[[2017,1,11]]},"abstract":"<jats:p>To promote FPGA to a wider user community and to increase design productivity, two new design methodologies, namely FPGA high-level synthesis (HLS) and FPGA overlay, are presented to use a high-level design abstraction. To make clear distinguish features of each design methodology, we make an comparison of a state-of-the-art FPGA HLS tool, Vivado HLS, and an FPGA overlay tool, ArchSyn, on two computation intensive kernels, matrix-matrix multiplication and fast Fourier transform.<\/jats:p>\n          <jats:p>In the comparison, FPGA overlay shows an overwhelming superiority in computation performance, which is 8X to 39X faster than FPGA HLS. However, FPGA HLS exhibits its advantages in dynamic power consumption metric. It achieves up to 17X lower power consumption than FPGA overlay. Power- and energy-efficiency are another two essential metrics evaluating trade-offs between performance and power consumption. As demonstrated with evaluation results, FPGA overlay is averagely 3.5X better in powerefficiency for FFT kernel, and achieves up to 2 orders of magnitude better energy-efficiency than FPGA HLS.<\/jats:p>","DOI":"10.1145\/3039902.3039919","type":"journal-article","created":{"date-parts":[[2017,1,17]],"date-time":"2017-01-17T13:42:08Z","timestamp":1484660528000},"page":"92-97","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":6,"title":["FPGA High-level Synthesis versus Overlay"],"prefix":"10.1145","volume":"44","author":[{"given":"Colin Yu","family":"Lin","sequence":"first","affiliation":[{"name":"Chinese Academy of Sciences"}]},{"given":"Zhenghong","family":"Jiang","sequence":"additional","affiliation":[{"name":"Chinese Academy of Sciences"}]},{"given":"Cheng","family":"Fu","sequence":"additional","affiliation":[{"name":"Chinese Academy of Sciences"}]},{"given":"Hayden Kwok-Hay","family":"So","sequence":"additional","affiliation":[{"name":"University of Hong Kong"}]},{"given":"Haigang","family":"Yang","sequence":"additional","affiliation":[{"name":"Chinese Academy of Sciences"}]}],"member":"320","published-online":{"date-parts":[[2017,1,11]]},"reference":[{"key":"e_1_2_1_1_1","first-page":"13","volume-title":"ISCA","author":"Putnam A.","year":"2014"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/2684746.2689060"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2011.62"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2011.2110592"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/1950413.1950423"},{"volume-title":"FPGAs for Software Engineers","year":"2016","author":"So H.K.H.","key":"e_1_2_1_6_1"},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/2460216.2460227"},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2013.6645515"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2015.15"},{"key":"e_1_2_1_10_1","unstructured":"Xilinx Inc. Vivado Design Suit User Guide High-Level Synthesis UG902 (v2016.1) http:\/\/www.xilinx.com\/support\/documentation\/sw_manuals\/xilinx2016_1\/ug902-vivado-high-level-synthesis.pdf 2016.  Xilinx Inc. Vivado Design Suit User Guide High-Level Synthesis UG902 (v2016.1) http:\/\/www.xilinx.com\/support\/documentation\/sw_manuals\/xilinx2016_1\/ug902-vivado-high-level-synthesis.pdf 2016."},{"key":"e_1_2_1_11_1","unstructured":"Y. Lin. ArchSyn: An Energy-efficient FPGA High-level Synthesizer. PhD thesis Univ. of Hong Kong Hong Kong http:\/\/hub.hku.hk\/bib\/B49799599 December 2012.  Y. Lin. ArchSyn: An Energy-efficient FPGA High-level Synthesizer. PhD thesis Univ. of Hong Kong Hong Kong http:\/\/hub.hku.hk\/bib\/B49799599 December 2012."},{"key":"e_1_2_1_12_1","unstructured":"Xilinx Inc. Vivado Design Suit User Guide Design Flows Overview UG892 (v2016.1) http:\/\/www.xilinx.com\/support\/documentation\/sw_manuals\/xilinx2016_1\/ug892-vivado-design-flows-overview.pdf 2016.  Xilinx Inc. Vivado Design Suit User Guide Design Flows Overview UG892 (v2016.1) http:\/\/www.xilinx.com\/support\/documentation\/sw_manuals\/xilinx2016_1\/ug892-vivado-design-flows-overview.pdf 2016."},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/2897937.2898040"}],"container-title":["ACM SIGARCH Computer Architecture News"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3039902.3039919","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3039902.3039919","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T03:36:31Z","timestamp":1750217791000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3039902.3039919"}},"subtitle":["Comparisons on Computation Kernels"],"short-title":[],"issued":{"date-parts":[[2017,1,11]]},"references-count":13,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2017,1,11]]}},"alternative-id":["10.1145\/3039902.3039919"],"URL":"https:\/\/doi.org\/10.1145\/3039902.3039919","relation":{},"ISSN":["0163-5964"],"issn-type":[{"type":"print","value":"0163-5964"}],"subject":[],"published":{"date-parts":[[2017,1,11]]},"assertion":[{"value":"2017-01-11","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}