{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,19]],"date-time":"2026-06-19T16:07:20Z","timestamp":1781885240867,"version":"3.54.5"},"reference-count":43,"publisher":"Association for Computing Machinery (ACM)","issue":"3","license":[{"start":{"date-parts":[[2017,5,27]],"date-time":"2017-05-27T00:00:00Z","timestamp":1495843200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"funder":[{"DOI":"10.13039\/100011102","name":"Seventh Framework Programme","doi-asserted-by":"publisher","award":["608224"],"award-info":[{"award-number":["608224"]}],"id":[{"id":"10.13039\/100011102","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100000266","name":"Engineering and Physical Sciences Research Council","doi-asserted-by":"publisher","award":["EP\/N508664\/-CSIT2"],"award-info":[{"award-number":["EP\/N508664\/-CSIT2"]}],"id":[{"id":"10.13039\/501100000266","id-type":"DOI","asserted-by":"publisher"}]},{"name":"IITP\/MSIP","award":["KeyHAS"],"award-info":[{"award-number":["KeyHAS"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Reconfigurable Technol. Syst."],"published-print":{"date-parts":[[2017,9,30]]},"abstract":"<jats:p>\n            Physical unclonable functions (PUFs), a form of physical security primitive, enable digital identifiers to be extracted from devices, such as field programmable gate arrays (FPGAs). Many PUF implementations have been proposed to generate these unique\n            <jats:italic>n<\/jats:italic>\n            -bit binary strings. However, they often offer insufficient uniqueness and reliability when implemented on FPGAs and can consume excessive resources. To address these problems, in this article we present an efficient, lightweight, and scalable PUF identification (ID) generator circuit that offers a compact design with good uniqueness and reliability properties and is specifically designed for FPGAs. A novel post-characterisation methodology is also proposed that improves the reliability of a PUF without the need for any additional hardware resources. Moreover, the proposed post-characterisation method can be generally used for any FPGA-based PUF designs. The PUF ID generator consumes 8.95% of the hardware resources of a low-cost Xilinx Spartan-6 LX9 FPGA and 0.81% of a Xilinx Artix-7 FPGA. Experimental results show good uniqueness, reliability, and uniformity with no occurrence of bit-aliasing. In particular, the reliability of the PUF is close to 100% over an environmental temperature range of 25\u00b0C to 70\u00b0C with \u00b1 10% variation in the supply voltage.\n          <\/jats:p>","DOI":"10.1145\/3053681","type":"journal-article","created":{"date-parts":[[2017,5,31]],"date-time":"2017-05-31T19:32:40Z","timestamp":1496259160000},"page":"1-23","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":61,"title":["Improved Reliability of FPGA-Based PUF Identification Generator Design"],"prefix":"10.1145","volume":"10","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-3028-8004","authenticated-orcid":false,"given":"Chongyan","family":"Gu","sequence":"first","affiliation":[{"name":"CSIT, ECIT, Queen's University Belfast, Queen's Road, United Kingdom, BT3 9DT"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Neil","family":"Hanley","sequence":"additional","affiliation":[{"name":"CSIT, ECIT, Queen's University Belfast, Queen's Road, United Kingdom, BT3 9DT"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"M\u00e1ire","family":"O'neill","sequence":"additional","affiliation":[{"name":"CSIT, ECIT, Queen's University Belfast, Queen's Road, United Kingdom, BT3 9DT"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2017,5,27]]},"reference":[{"key":"e_1_2_1_1_1","volume-title":"The Gap Between Promise and Reality: On the Insecurity of XOR Arbiter PUFs","author":"Becker Georg T."},{"key":"e_1_2_1_2_1","volume-title":"Proceedings of the ACM\/IEEE Design, Automation and Test in Europe Conference and Exhibition (DATE\u201914)","author":"Bhargava Mudit","year":"2014"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICNSS.2011.6060013"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/PERCOM.2007.26"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/HST.2011.5955011"},{"key":"e_1_2_1_6_1","volume-title":"Proceedings of the IEEE International Symposium on Hardware-Oriented Security and Trust (HOST\u201913)","author":"Cortez Mafalda"},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2013.2290845"},{"key":"e_1_2_1_8_1","volume-title":"Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS\u201914)","author":"Gary Achiranshu","year":"1941"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/586110.586132"},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/SOCC.2016.7905439"},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2014.6865362"},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2015.7168788"},{"key":"e_1_2_1_13_1","doi-asserted-by":"crossref","volume-title":"FPGA Intrinsic PUFs and Their Use for IP Protection","author":"Guajardo Jorge","DOI":"10.1007\/978-3-540-74735-2_5"},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2014.2320516"},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2008.212"},{"key":"e_1_2_1_16_1","volume-title":"DRV-Fingerprinting: Using Data Retention Voltage of SRAM Cells for Chip Identification","author":"Holcomb Daniel E."},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.2197\/ipsjjip.22.344"},{"key":"e_1_2_1_18_1","volume-title":"Retrieved","author":"June ID.","year":"2015"},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1109\/HST.2014.6855565"},{"key":"e_1_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/HST.2008.4559053"},{"key":"e_1_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1109\/HST.2009.5225058"},{"key":"e_1_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2005.859470"},{"key":"e_1_2_1_23_1","volume-title":"Proceedings of the 3rd Benelux Workshop on Information and System Security (WISSec\u201908)","author":"Maes Roel","year":"2008"},{"key":"e_1_2_1_24_1","first-page":"632","article-title":"Combined modeling and side channel attacks on strong PUFs","volume":"2013","author":"Mahmoud Ahmed","year":"2013","journal-title":"IACR Cryptology ePrint Archive"},{"key":"e_1_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1109\/TIFS.2011.2165540"},{"key":"e_1_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2012.6339208"},{"key":"e_1_2_1_27_1","first-page":"639","article-title":"Automated design, implementation, and evaluation of arbiter-based PUF on FPGA using programmable delay lines","volume":"2014","author":"Majzoobi Mehrdad","year":"2014","journal-title":"IACR Cryptology ePrint Archive"},{"key":"e_1_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1145\/1873548.1873557"},{"key":"e_1_2_1_29_1","volume-title":"Microsemi SmartFusion2 SoC FPGAs Offer More Resources in Low Density Devices With The Lowest Power, Proven Security and Exceptional Reliability. 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