{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:07:27Z","timestamp":1750306047744,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":19,"publisher":"ACM","license":[{"start":{"date-parts":[[2017,5,10]],"date-time":"2017-05-10T00:00:00Z","timestamp":1494374400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/100010663","name":"H2020 European Research Council","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100010663","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2017,5,10]]},"DOI":"10.1145\/3060403.3060432","type":"proceedings-article","created":{"date-parts":[[2017,5,16]],"date-time":"2017-05-16T19:56:07Z","timestamp":1494964567000},"page":"131-136","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":3,"title":["Improving Circuit Mapping Performance Through MIG-based Synthesis for Carry Chains"],"prefix":"10.1145","author":[{"given":"Zhufei","family":"Chu","sequence":"first","affiliation":[{"name":"Ningbo University & \u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne, Ningbo, China"}]},{"given":"Xifan","family":"Tang","sequence":"additional","affiliation":[{"name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne, Lausanne, Switzerland"}]},{"given":"Mathias","family":"Soeken","sequence":"additional","affiliation":[{"name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne, Lausanne, Switzerland"}]},{"given":"Ana","family":"Petkovska","sequence":"additional","affiliation":[{"name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne, Lausanne, Switzerland"}]},{"given":"Grace","family":"Zgheib","sequence":"additional","affiliation":[{"name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne, Lausanne, Switzerland"}]},{"given":"Luca","family":"Amar\u00f9","sequence":"additional","affiliation":[{"name":"Synopsys Inc., Sunnyvale, USA"}]},{"given":"Yinshui","family":"Xia","sequence":"additional","affiliation":[{"name":"Ningbo University, Ningbo, China"}]},{"given":"Paolo","family":"Ienne","sequence":"additional","affiliation":[{"name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne, Lausanne, Switzerland"}]},{"given":"Giovanni","family":"De Micheli","sequence":"additional","affiliation":[{"name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne, Lausanne, Switzerland"}]},{"given":"Pierre-Emmanuel","family":"Gaillardon","sequence":"additional","affiliation":[{"name":"University of Utah, Salt Lake City, UT, USA"}]}],"member":"320","published-online":{"date-parts":[[2017,5,10]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.5555\/2650280.2650384"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/2593069.2593158"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2488484"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-14295-6_5"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1986.1676819"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.5555\/553523"},{"key":"e_1_3_2_1_7_1","first-page":"135","volume-title":"FPL","author":"M.","year":"2004","unstructured":"M. Hutton phet al. Improving FPGA performance and area using an adaptive logic module. In FPL, pages 135--144, 2004."},{"volume-title":"Stratix 10 advance information brief","year":"2015","key":"e_1_3_2_1_8_1","unstructured":"Altera. Stratix 10 advance information brief. Altera Corporation, July 2015."},{"volume-title":"May","year":"2015","key":"e_1_3_2_1_9_1","unstructured":"Xilinx. Virtex-7 user guide DS180 (v1.17). Xilinx, May 2015."},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.5555\/541643"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/1344671.1344679"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2010.70"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2015.7393133"},{"key":"e_1_3_2_1_14_1","first-page":"165","volume-title":"SASIMI","author":"Amar\u00f9 L.","year":"2015","unstructured":"L. Amar\u00f9, A. Petkovska, P.-E. Gaillardon, D. Novo, P. Ienne, and G. De Micheli. Majority-inverter graph for FPGA synthesis. In SASIMI, pages 165--170, 2015."},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/2145694.2145708"},{"key":"e_1_3_2_1_16_1","unstructured":"Berkeley Logic Synthesis and Verification Group ABC: A system for sequential synthesis and verification http:\/\/www.eecs.berkeley.edu\/ alanmi\/abc\/."},{"key":"e_1_3_2_1_17_1","volume-title":"NANOARCH","author":"Testa E.","year":"2016","unstructured":"E. Testa, M. Soeken, O. Zografos, L. Amar\u00f9, P. Raghavan, R. Lauwereins, P.-E. Gaillardon, and G. De Micheli. Inversion optimization in majority-inverter graphs. In NANOARCH, 2016."},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/201310.201322"},{"key":"e_1_3_2_1_19_1","volume-title":"ASPDAC","author":"Haaswijk W.","year":"2017","unstructured":"W. Haaswijk, M. Soeken, L. Amar\u00f9, P.-E. Gaillardon, and G. De Micheli. A novel basis for logic rewriting. In ASPDAC, 2017."}],"event":{"name":"GLSVLSI '17: Great Lakes Symposium on VLSI 2017","sponsor":["SIGDA ACM Special Interest Group on Design Automation","IEEE CEDA","IEEE CASS"],"location":"Banff Alberta Canada","acronym":"GLSVLSI '17"},"container-title":["Proceedings of the Great Lakes Symposium on VLSI 2017"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3060403.3060432","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3060403.3060432","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T03:03:20Z","timestamp":1750215800000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3060403.3060432"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,5,10]]},"references-count":19,"alternative-id":["10.1145\/3060403.3060432","10.1145\/3060403"],"URL":"https:\/\/doi.org\/10.1145\/3060403.3060432","relation":{},"subject":[],"published":{"date-parts":[[2017,5,10]]},"assertion":[{"value":"2017-05-10","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}