{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,19]],"date-time":"2026-06-19T16:39:13Z","timestamp":1781887153487,"version":"3.54.5"},"reference-count":18,"publisher":"Association for Computing Machinery (ACM)","issue":"4","license":[{"start":{"date-parts":[[2017,5,21]],"date-time":"2017-05-21T00:00:00Z","timestamp":1495324800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/100000028","name":"Semiconductor Research Corporation","doi-asserted-by":"publisher","award":["2442.001"],"award-info":[{"award-number":["2442.001"]}],"id":[{"id":"10.13039\/100000028","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","award":["CNS-1441757"],"award-info":[{"award-number":["CNS-1441757"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["J. Emerg. Technol. Comput. Syst."],"published-print":{"date-parts":[[2017,10,31]]},"abstract":"<jats:p>Content Addressable Memory (CAM) is widely used in applications where searching a specific pattern of data is a major operation. Conventional CAMs suffer from area, power, and speed limitations. We propose Spin-Torque Transfer RAM--based Ternary CAM (TCAM) cells. The proposed NOR-type TCAM cell has a 62.5% (33%) reduction in number of transistor compared to conventional CMOS TCAMs (spintronic TCAMs). We analyzed the sense margin of the proposed TCAM with respect to 16-, 32-, 64-, 128-, and 256-bit word sizes in 22nm predictive technology. Simulations indicated a reliable sense margin of 50mV even at 0.7V supply voltage for 256-bits word. We also explored a selective threshold voltage modulation of transistors to improve the sense margin and tolerate process and voltage variations. The worst-case search latency and sense margin of 256-bit TCAM is found to be 263ps and 220mV, respectively, at 1V supply voltage. The average search power consumed is 13mW, and the search energy is 4.7fJ\/bit search. The write time is 4ns, and the write energy is 0.69pJ\/bit. We leverage the NOR-type TCAM design to realize a 9T-2 Magnetic Tunnel Junctions NAND-type TCAM cell that has 43.75% less number of transistors than the conventional CMOS TCAM cell. A NAND-type cell can support up to 64-bit words with a maximum sense margin of up to 33mV. We compare the performance metrics of NOR- and NAND-type TCAM cells with other TCAMs in the literature.<\/jats:p>","DOI":"10.1145\/3060578","type":"journal-article","created":{"date-parts":[[2017,5,22]],"date-time":"2017-05-22T12:20:31Z","timestamp":1495455631000},"page":"1-22","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":17,"title":["Design and Analysis of STTRAM-Based Ternary Content Addressable Memory Cell"],"prefix":"10.1145","volume":"13","author":[{"given":"Rekha","family":"Govindaraj","sequence":"first","affiliation":[{"name":"University of South Florida, Tampa, FL"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Swaroop","family":"Ghosh","sequence":"additional","affiliation":[{"name":"Pennsylvania State University, State College, PA"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2017,5,21]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.864128"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1063\/1.2201547"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2008.4541813"},{"key":"e_1_2_1_4_1","volume-title":"Proceedings of the 2011 Symposium on VLSI Circuits (VLSIC). IEEE, 300--301","author":"Nebashi R."},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/TMAG.2012.2198876"},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/NANO.2013.6720805"},{"key":"e_1_2_1_7_1","unstructured":"X. Fong S. H. Choday P. Georgios C. Augustine and K. Roy. 2013. SPICE models for magnetic tunnel junctions based on monodomain approximation.  X. Fong S. H. Choday P. Georgios C. Augustine and K. Roy. 2013. SPICE models for magnetic tunnel junctions based on monodomain approximation."},{"key":"e_1_2_1_8_1","unstructured":"X. Wang. (Ed.). 2014. Metallic Spintronic Devices. CRC Press.  X. Wang. (Ed.). 2014. Metallic Spintronic Devices. CRC Press."},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2224256"},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2012.6243781"},{"key":"e_1_2_1_11_1","unstructured":"Y. U. Cao T. Sato D. Sylvester M. Orshansky and C. Hu. 2002. Predictive technology model. Retrieved from http:\/\/ptm.asu.edu.  Y. U. Cao T. Sato D. Sylvester M. Orshansky and C. Hu. 2002. Predictive technology model. Retrieved from http:\/\/ptm.asu.edu."},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISLPED.2015.7273532"},{"key":"e_1_2_1_13_1","doi-asserted-by":"crossref","unstructured":"R. Govindaraj I. Sengupta and S. Chattopadhyay. 2012. An efficient technique for longest prefix matching in network routers. In Progress in VLSI Design and Test. Springer Berlin Heidelberg 317--326.  R. Govindaraj I. Sengupta and S. Chattopadhyay. 2012. An efficient technique for longest prefix matching in network routers. In Progress in VLSI Design and Test. Springer Berlin Heidelberg 317--326.","DOI":"10.1007\/978-3-642-31494-0_36"},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2015.2434888"},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/2206781.2206857"},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2292055"},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/1146909.1147155"},{"key":"e_1_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1587\/elex.11.20131006"}],"container-title":["ACM Journal on Emerging Technologies in Computing Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3060578","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3060578","content-type":"application\/pdf","content-version":"vor","intended-application":"syndication"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3060578","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T03:03:21Z","timestamp":1750215801000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3060578"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,5,21]]},"references-count":18,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2017,10,31]]}},"alternative-id":["10.1145\/3060578"],"URL":"https:\/\/doi.org\/10.1145\/3060578","relation":{},"ISSN":["1550-4832","1550-4840"],"issn-type":[{"value":"1550-4832","type":"print"},{"value":"1550-4840","type":"electronic"}],"subject":[],"published":{"date-parts":[[2017,5,21]]},"assertion":[{"value":"2016-06-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2016-12-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2017-05-21","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}