{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,21]],"date-time":"2025-06-21T04:05:51Z","timestamp":1750478751511,"version":"3.41.0"},"reference-count":23,"publisher":"Association for Computing Machinery (ACM)","issue":"4","license":[{"start":{"date-parts":[[2017,6,29]],"date-time":"2017-06-29T00:00:00Z","timestamp":1498694400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["J. Emerg. Technol. Comput. Syst."],"published-print":{"date-parts":[[2017,10,31]]},"abstract":"<jats:p>Near-threshold computing (NTC) circuits have been shown to offer significant energy efficiency and power benefits but with a huge performance penalty. This performance loss exacerbates if process and voltage variations are considered. In this article, we demonstrate that three-dimensional (3D) IC technology can overcome this limitation. We present a detailed case study with a 28nm commercial-grade core at 0.6V operation optimized with various 3D IC physical design methods. First, our study under the deterministic case shows that 3D IC NTC design outperforms 2D IC NTC by 29.5% in terms of performance at comparable energy. This is significantly higher than the 12.8% performance benefit of 3D IC at nominal voltage supplies due to higher delay sensitivity to input slew at lower voltages. Second, it is well demonstrated that transistor delay is more sensitive to voltage changes at NTC operation. However, our full-chip study reveals that IR drop effect on 2D\/3D IC NTC performance is not severe due to the low power consumption and hence lower IR drop values. Third, die-to-die variation impact on full-chip performance is visible in 3D IC NTC designs, but it is not worse compared to 2D IC NTC designs. This is mainly due to the shorter critical path length in 3D IC NTC designs.<\/jats:p>","DOI":"10.1145\/3060579","type":"journal-article","created":{"date-parts":[[2017,6,30]],"date-time":"2017-06-30T12:36:19Z","timestamp":1498826179000},"page":"1-18","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":1,"title":["Improving Performance under Process and Voltage Variations in Near-Threshold Computing Using 3D ICs"],"prefix":"10.1145","volume":"13","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-2636-9928","authenticated-orcid":false,"given":"Sandeep Kumar","family":"Samal","sequence":"first","affiliation":[{"name":"Georgia Institute of Technology, Atlanta, GA"}]},{"given":"Guoqing","family":"Chen","sequence":"additional","affiliation":[{"name":"Advanced Micro Devices"}]},{"given":"Sung Kyu","family":"Lim","sequence":"additional","affiliation":[{"name":"Georgia Institute of Technology, Atlanta, GA"}]}],"member":"320","published-online":{"date-parts":[[2017,6,29]]},"reference":[{"volume-title":"2013 Proceedings of the ESSCIRC (ESSCIRC). 205--208","author":"Abouzeid F.","key":"e_1_2_1_1_1","unstructured":"F. Abouzeid , A. Bienfait , K. C. Akyel , S. Clerc , L. Ciampolini , and P. Roche . 2013. Scalable 0.35V to 1.2V SRAM bitcell design from 65nm CMOS to 28nm FDSOI . In 2013 Proceedings of the ESSCIRC (ESSCIRC). 205--208 . F. Abouzeid, A. Bienfait, K. C. Akyel, S. Clerc, L. Ciampolini, and P. Roche. 2013. Scalable 0.35V to 1.2V SRAM bitcell design from 65nm CMOS to 28nm FDSOI. In 2013 Proceedings of the ESSCIRC (ESSCIRC). 205--208."},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2006.887809"},{"key":"e_1_2_1_3_1","volume-title":"Automation Test in Europe Conference Exhibition (DATE)","author":"Beigne E.","year":"2013","unstructured":"E. Beigne , A. Valentian , B. Giraud , O. Thomas , T. Benoist , Y. Thonnart , S. Bernard , G. Moritz , O. Billoint , Y. Maneglia , P. Flatresse , J. P. Noel , F. Abouzeid , B. Pelloux-Prayer , A. Grover , S. Clerc , P. Roche , J. Le Coz , S. Engels , and R. Wilson . 2013. Ultra-wide voltage range designs in fully-depleted silicon-on-insulator FETs. In Design , Automation Test in Europe Conference Exhibition (DATE) , 2013 . 613--618. E. Beigne, A. Valentian, B. Giraud, O. Thomas, T. Benoist, Y. Thonnart, S. Bernard, G. Moritz, O. Billoint, Y. Maneglia, P. Flatresse, J. P. Noel, F. Abouzeid, B. Pelloux-Prayer, A. Grover, S. Clerc, P. Roche, J. Le Coz, S. Engels, and R. Wilson. 2013. Ultra-wide voltage range designs in fully-depleted silicon-on-insulator FETs. In Design, Automation Test in Europe Conference Exhibition (DATE), 2013. 613--618."},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2009.2033621"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2009.2035451"},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2015.7357157"},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2009.2034764"},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.5555\/1299042.1299046"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2222814"},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2009.4810285"},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.5555\/1167704.1167714"},{"key":"e_1_2_1_12_1","doi-asserted-by":"crossref","unstructured":"Da-Cheng Juan S. Garg and D. Marculescu. 2013. Impact of manufacturing process variations on performance and thermal characteristics of 3D ICs: Emerging challenges and new solutions. In ISCAS. Da-Cheng Juan S. Garg and D. Marculescu. 2013. Impact of manufacturing process variations on performance and thermal characteristics of 3D ICs: Emerging challenges and new solutions. In ISCAS.","DOI":"10.1109\/ISCAS.2013.6571900"},{"key":"e_1_2_1_13_1","first-page":"10","article-title":"Fine-grained 3-D IC partitioning study with a multicore processor","volume":"5","author":"Jung Moongon","year":"2015","unstructured":"Moongon Jung , Taigon Song , Yarui Peng , and Sung Kyu Lim . 2015 . Fine-grained 3-D IC partitioning study with a multicore processor . IEEE Trans. Comp. Packag. Manuf. Technol. 5 , 10 (Oct 2015), 1393--1401. Moongon Jung, Taigon Song, Yarui Peng, and Sung Kyu Lim. 2015. Fine-grained 3-D IC partitioning study with a multicore processor. IEEE Trans. Comp. Packag. Manuf. Technol. 5, 10 (Oct 2015), 1393--1401.","journal-title":"IEEE Trans. Comp. Packag. Manuf. Technol."},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2009.2034508"},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228572"},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2013.6487801"},{"key":"e_1_2_1_17_1","volume-title":"2013 14th International Symposium on Quality Electronic Design (ISQED). 300--307","author":"Liu Wulong","year":"2013","unstructured":"Wulong Liu , Haixiao Du , Yu Wang , Yuchun Ma , Y. Xie , Jinguo Quan , and Huazhong Yang . 2013 . TSV-aware topology generation for 3D clock tree synthesis . In 2013 14th International Symposium on Quality Electronic Design (ISQED). 300--307 . Wulong Liu, Haixiao Du, Yu Wang, Yuchun Ma, Y. Xie, Jinguo Quan, and Huazhong Yang. 2013. TSV-aware topology generation for 3D clock tree synthesis. In 2013 14th International Symposium on Quality Electronic Design (ISQED). 300--307."},{"key":"e_1_2_1_18_1","doi-asserted-by":"crossref","unstructured":"Chien-Wei Lo Liang Men J. Brady and Jia Di. 2015. Asynchronous and synchronous designs for low-power FDSOI CMOS process optimized for subthreshold operation at 0.3V VDD. In 2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S). 1--3. Chien-Wei Lo Liang Men J. Brady and Jia Di. 2015. Asynchronous and synchronous designs for low-power FDSOI CMOS process optimized for subthreshold operation at 0.3V VDD. In 2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S). 1--3.","DOI":"10.1109\/S3S.2015.7333511"},{"key":"e_1_2_1_19_1","unstructured":"OpenSPARC T2 Oracle. 2014. http:\/\/www.oracle.com. (2014). OpenSPARC T2 Oracle. 2014. http:\/\/www.oracle.com. (2014)."},{"key":"e_1_2_1_20_1","doi-asserted-by":"crossref","unstructured":"S. K. Samal Y. Li G. Chen and S. K. Lim. 2015a. Improving performance in near-threshold circuits using 3D IC technology. In 2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S). 1--2. S. K. Samal Y. Li G. Chen and S. K. Lim. 2015a. Improving performance in near-threshold circuits using 3D IC technology. In 2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S). 1--2.","DOI":"10.1109\/S3S.2015.7333541"},{"key":"e_1_2_1_21_1","first-page":"7","article-title":"Ultralow power circuit design with subthreshold\/near-threshold 3-D IC technologies","volume":"5","author":"Samal S. K.","year":"2015","unstructured":"S. K. Samal , Y. Peng , M. Pathak , and S. K. Lim . 2015 b. Ultralow power circuit design with subthreshold\/near-threshold 3-D IC technologies . IEEE Trans. Comp. Packag. Manuf. Technol. 5 , 7 (Jul. 2015), 980--990. S. K. Samal, Y. Peng, M. Pathak, and S. K. Lim. 2015b. Ultralow power circuit design with subthreshold\/near-threshold 3-D IC technologies. IEEE Trans. Comp. Packag. Manuf. Technol. 5, 7 (Jul. 2015), 980--990.","journal-title":"IEEE Trans. Comp. Packag. Manuf. Technol."},{"volume-title":"2011 16th Asia and South Pacific Design Automation Conference (ASP-DAC). 621--626","author":"Yang J. S.","key":"e_1_2_1_22_1","unstructured":"J. S. Yang , J. Pak , X. Zhao , S. K. Lim , and D. Z. Pan . 2011. Robust clock tree synthesis with timing yield optimization for 3D-ICs . In 2011 16th Asia and South Pacific Design Automation Conference (ASP-DAC). 621--626 . J. S. Yang, J. Pak, X. Zhao, S. K. Lim, and D. Z. Pan. 2011. Robust clock tree synthesis with timing yield optimization for 3D-ICs. In 2011 16th Asia and South Pacific Design Automation Conference (ASP-DAC). 621--626."},{"key":"e_1_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1145\/1283780.1283789"}],"container-title":["ACM Journal on Emerging Technologies in Computing Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3060579","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3060579","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,20]],"date-time":"2025-06-20T18:52:04Z","timestamp":1750445524000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3060579"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,6,29]]},"references-count":23,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2017,10,31]]}},"alternative-id":["10.1145\/3060579"],"URL":"https:\/\/doi.org\/10.1145\/3060579","relation":{},"ISSN":["1550-4832","1550-4840"],"issn-type":[{"type":"print","value":"1550-4832"},{"type":"electronic","value":"1550-4840"}],"subject":[],"published":{"date-parts":[[2017,6,29]]},"assertion":[{"value":"2016-09-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2017-02-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2017-06-29","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}