{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:08:36Z","timestamp":1750306116252,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":23,"publisher":"ACM","license":[{"start":{"date-parts":[[2017,6,18]],"date-time":"2017-06-18T00:00:00Z","timestamp":1497744000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/100000015","name":"U.S. Department of Energy","doi-asserted-by":"publisher","award":["DE-SC0012531"],"award-info":[{"award-number":["DE-SC0012531"]}],"id":[{"id":"10.13039\/100000015","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","award":["CCF-1422489"],"award-info":[{"award-number":["CCF-1422489"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2017,6,18]]},"DOI":"10.1145\/3061639.3062197","type":"proceedings-article","created":{"date-parts":[[2017,6,13]],"date-time":"2017-06-13T12:18:42Z","timestamp":1497356322000},"page":"1-6","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":6,"title":["Adaptive Thermal Management for 3D ICs with Stacked DRAM Caches"],"prefix":"10.1145","author":[{"given":"Dawei","family":"Li","sequence":"first","affiliation":[{"name":"Department of EECS, Northwestern University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kaicheng","family":"Zhang","sequence":"additional","affiliation":[{"name":"Department of EECS, Northwestern University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Akhil","family":"Guliani","sequence":"additional","affiliation":[{"name":"Department of EECS, Northwestern University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Seda","family":"Ogrenci-Memik","sequence":"additional","affiliation":[{"name":"Department of EECS, Northwestern University"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2017,6,18]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"Hybrid Memory Cube: http:\/\/www.hybridmemorycube.org\/technology.html.  Hybrid Memory Cube: http:\/\/www.hybridmemorycube.org\/technology.html."},{"key":"e_1_3_2_1_2_1","unstructured":"Tezzaron Semiconductor \"Octopus 8-port DRAM for die-stack applications\" May 2010.  Tezzaron Semiconductor \"Octopus 8-port DRAM for die-stack applications\" May 2010."},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2015.7357156"},{"key":"e_1_3_2_1_4_1","volume-title":"Heterogeneous Memory Management for 3D-DRAM external DRAM with QoS","author":"Tran L.-N.","year":"2013","unstructured":"L.-N. Tran , , \" Heterogeneous Memory Management for 3D-DRAM external DRAM with QoS \", IEEE ASP-DAC , 2013 . L.-N. Tran, et al., \"Heterogeneous Memory Management for 3D-DRAM external DRAM with QoS\", IEEE ASP-DAC, 2013."},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/1394608.1382159"},{"key":"e_1_3_2_1_6_1","volume-title":"3D DRAM Design and Application to 3D Multicore Systems","author":"Sun H.","year":"2009","unstructured":"H. Sun , , \" 3D DRAM Design and Application to 3D Multicore Systems \", IEEE CD & CASS , 2009 . H. Sun, et al., \"3D DRAM Design and Application to 3D Multicore Systems\", IEEE CD & CASS, 2009."},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/2508148.2485957"},{"key":"e_1_3_2_1_8_1","volume-title":"Design of controller for L2 cache mapped in Tezzaron stacked DRAM.\" IEEE 3D Systems Integration Conference (3DIC)","author":"Tshibangu N. M.","year":"2013","unstructured":"N. M. Tshibangu , \" Design of controller for L2 cache mapped in Tezzaron stacked DRAM.\" IEEE 3D Systems Integration Conference (3DIC) , 2013 N. M. Tshibangu, et al. \"Design of controller for L2 cache mapped in Tezzaron stacked DRAM.\" IEEE 3D Systems Integration Conference (3DIC), 2013"},{"key":"e_1_3_2_1_9_1","volume-title":"Three-Dimensional Integrated Circuit Design --Chapter 3","author":"Jain P.","year":"2010","unstructured":"P. Jain , , \" Thermal and Power Delivery Challenges in 3D ICs \", Three-Dimensional Integrated Circuit Design --Chapter 3 , Y. Xie et al.(eds.), Integrated Circuits and Systems, Springer , 2010 . P. Jain, et al., \"Thermal and Power Delivery Challenges in 3D ICs\", Three-Dimensional Integrated Circuit Design --Chapter 3, Y. Xie et al.(eds.), Integrated Circuits and Systems, Springer, 2010."},{"key":"e_1_3_2_1_10_1","volume-title":"IET","author":"Ogrenci-Memik S.","year":"2015","unstructured":"S. Ogrenci-Memik , Heat Management in Integrated Circuits : On-chip and System-level Monitoring and Cooling . IET , 2015 . S. Ogrenci-Memik, Heat Management in Integrated Circuits: On-chip and System-level Monitoring and Cooling. IET, 2015."},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2012.29"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/2024724.2024876"},{"key":"e_1_3_2_1_13_1","volume-title":"Integrating Thermocouple Sensors into 3D ICs","author":"Li D.","year":"2013","unstructured":"D. Li , , \" Integrating Thermocouple Sensors into 3D ICs \", IEEE ICCD , 2013 D. Li, et al., \"Integrating Thermocouple Sensors into 3D ICs\", IEEE ICCD, 2013"},{"key":"e_1_3_2_1_14_1","volume-title":"IEEE ECTC","author":"Pi Y.","year":"2016","unstructured":"Y. Pi , Cooling for distributed hot-spots \", IEEE ECTC , 2016 . Y. Pi, et al., \"Microfluidic Cooling for distributed hot-spots\", IEEE ECTC, 2016."},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1038\/nnano.2008.417"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2015.2417540"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228477"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2009.30"},{"key":"e_1_3_2_1_19_1","unstructured":"NAS Division. NAS parallel benchmarks. http:\/\/www.nas.nasa.gov\/Resources\/Software\/npb.html.  NAS Division. NAS parallel benchmarks. http:\/\/www.nas.nasa.gov\/Resources\/Software\/npb.html."},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669172"},{"key":"e_1_3_2_1_21_1","volume-title":"IEEE HPCA","author":"Liu S.","year":"2011","unstructured":"S. Liu , B. Leung , A. Neckar , S. Ogrenci-Memik , G. Memik , N. Hardavellas , \"Hardware\/software techniques for DRAM thermal management \", IEEE HPCA , 2011 S. Liu, B. Leung, A. Neckar, S. Ogrenci-Memik, G. Memik, N. Hardavellas, \"Hardware\/software techniques for DRAM thermal management\", IEEE HPCA, 2011"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/1391469.1391691"},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2009.2014842"}],"event":{"name":"DAC '17: The 54th Annual Design Automation Conference 2017","sponsor":["EDAC Electronic Design Automation Consortium","SIGDA ACM Special Interest Group on Design Automation","IEEE-CEDA","SIGBED ACM Special Interest Group on Embedded Systems"],"location":"Austin TX USA","acronym":"DAC '17"},"container-title":["Proceedings of the 54th Annual Design Automation Conference 2017"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3061639.3062197","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3061639.3062197","content-type":"application\/pdf","content-version":"vor","intended-application":"syndication"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3061639.3062197","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T03:36:34Z","timestamp":1750217794000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3061639.3062197"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,6,18]]},"references-count":23,"alternative-id":["10.1145\/3061639.3062197","10.1145\/3061639"],"URL":"https:\/\/doi.org\/10.1145\/3061639.3062197","relation":{},"subject":[],"published":{"date-parts":[[2017,6,18]]},"assertion":[{"value":"2017-06-18","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}