{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,24]],"date-time":"2025-10-24T16:41:45Z","timestamp":1761324105458,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":19,"publisher":"ACM","license":[{"start":{"date-parts":[[2017,6,18]],"date-time":"2017-06-18T00:00:00Z","timestamp":1497744000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","award":["1527464"],"award-info":[{"award-number":["1527464"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2017,6,18]]},"DOI":"10.1145\/3061639.3062198","type":"proceedings-article","created":{"date-parts":[[2017,6,13]],"date-time":"2017-06-13T12:18:42Z","timestamp":1497356322000},"page":"1-6","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":14,"title":["Age-aware Logic and Memory Co-Placement for RRAM-FPGAs"],"prefix":"10.1145","author":[{"given":"Yuan","family":"Xue","sequence":"first","affiliation":[{"name":"University of Delaware"}]},{"given":"Chengmo","family":"Yang","sequence":"additional","affiliation":[{"name":"University of Delaware"}]},{"given":"Jingtong","family":"Hu","sequence":"additional","affiliation":[{"name":"Oklahoma State University"}]}],"member":"320","published-online":{"date-parts":[[2017,6,18]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"UltraScale Architecture and Product Overview Xilinx 2016.  UltraScale Architecture and Product Overview Xilinx 2016."},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.884574"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2013.2259512"},{"key":"e_1_3_2_1_4_1","first-page":"38","article-title":"STRAP: Stress-aware placement for aging mitigation in runtime reconfigurable architectures","author":"Zhang H.","year":"2015","unstructured":"H. Zhang , M. A. Kochte , E. Schneider , L. Bauer , H.-J. Wunderlich , and J. Henkel , \" STRAP: Stress-aware placement for aging mitigation in runtime reconfigurable architectures ,\" in ICCAD , 2015 , pp. 38 -- 45 . H. Zhang, M. A. Kochte, E. Schneider, L. Bauer, H.-J. Wunderlich, and J. Henkel, \"STRAP: Stress-aware placement for aging mitigation in runtime reconfigurable architectures,\" in ICCAD, 2015, pp. 38--45.","journal-title":"ICCAD"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/2617593"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/1840845.1840857"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/1596543.1596548"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2012.2226747"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"crossref","unstructured":"H.-S. P. Wong H.-Y. Lee S. Yu Y.-S. Chen Y. Wu P.-S. Chen B. Lee F. T. Chen and M.-J. Tsai \"Metal-oxide RRAM \" Proceedings of the IEEE vol. 100 May. 2012.  H.-S. P. Wong H.-Y. Lee S. Yu Y.-S. Chen Y. Wu P.-S. Chen B. Lee F. T. Chen and M.-J. Tsai \"Metal-oxide RRAM \" Proceedings of the IEEE vol. 100 May. 2012.","DOI":"10.1109\/JPROC.2012.2190369"},{"key":"e_1_3_2_1_10_1","first-page":"367","article-title":"Non-volatile 3D stacking RRAM-based FPGA","author":"Chen Y.-C.","year":"2012","unstructured":"Y.-C. Chen , W. Wang , H. Li , and W. Zhang , \" Non-volatile 3D stacking RRAM-based FPGA ,\" in FPL , 2012 , pp. 367 -- 372 . Y.-C. Chen, W. Wang, H. Li, and W. Zhang, \"Non-volatile 3D stacking RRAM-based FPGA,\" in FPL, 2012, pp. 367--372.","journal-title":"FPL"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2010.88"},{"key":"e_1_3_2_1_12_1","first-page":"1","article-title":"Module diversification: Fault tolerance and aging mitigation for runtime reconfigurable architectures","author":"Zhang H.","year":"2013","unstructured":"H. Zhang , L. Bauer , M. A. Kochte , E. Schneider , C. Braun , M. E. Imhof , H.-J. Wunderlich , and J. Henkel , \" Module diversification: Fault tolerance and aging mitigation for runtime reconfigurable architectures ,\" in ITC , 2013 , pp. 1 -- 10 . H. Zhang, L. Bauer, M. A. Kochte, E. Schneider, C. Braun, M. E. Imhof, H.-J. Wunderlich, and J. Henkel, \"Module diversification: Fault tolerance and aging mitigation for runtime reconfigurable architectures,\" in ITC, 2013, pp. 1--10.","journal-title":"ITC"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2011.56"},{"key":"e_1_3_2_1_14_1","first-page":"1","article-title":"Fine-tuning CLB placement to speed up reconfigurations in NVM-based FPGAs","author":"Xue Y.","year":"2015","unstructured":"Y. Xue , P. Cronin , C. Yang , and J. Hu , \" Fine-tuning CLB placement to speed up reconfigurations in NVM-based FPGAs ,\" in FPL , 2015 , pp. 1 -- 8 . Y. Xue, P. Cronin, C. Yang, and J. Hu, \"Fine-tuning CLB placement to speed up reconfigurations in NVM-based FPGAs,\" in FPL, 2015, pp. 1--8.","journal-title":"FPL"},{"key":"e_1_3_2_1_15_1","volume-title":"Oct.","author":"Xue Y.","year":"2015","unstructured":"Y. Xue , P. Cronin , C. Yang , and J. Hu , \" Non-volatile memories in FPGAs: Exploiting logic similarity to accelerate reconfiguration and increase programming cycles,\" in VLSI-SoC , Oct. 2015 . Y. Xue, P. Cronin, C. Yang, and J. Hu, \"Non-volatile memories in FPGAs: Exploiting logic similarity to accelerate reconfiguration and increase programming cycles,\" in VLSI-SoC, Oct. 2015."},{"key":"e_1_3_2_1_16_1","first-page":"360","article-title":"Routing path reuse maximization for efficient NV-FPGA reconfiguration","author":"Xue Y.","year":"2016","unstructured":"Y. Xue , P. Cronin , C. Yang , and J. Hu , \" Routing path reuse maximization for efficient NV-FPGA reconfiguration ,\" in ASP-DAC , 2016 , pp. 360 -- 365 . Y. Xue, P. Cronin, C. Yang, and J. Hu, \"Routing path reuse maximization for efficient NV-FPGA reconfiguration,\" in ASP-DAC, 2016, pp. 360--365.","journal-title":"ASP-DAC"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"crossref","unstructured":"A. Naamad D. Lee and W.-L. Hsu \"On the maximum empty rectangle problem \" Discrete Applied Mathematics vol. 8 Jul. 1984.  A. Naamad D. Lee and W.-L. Hsu \"On the maximum empty rectangle problem \" Discrete Applied Mathematics vol. 8 Jul. 1984.","DOI":"10.1016\/0166-218X(84)90124-0"},{"key":"e_1_3_2_1_18_1","first-page":"381","article-title":"An efficient general cooling schedule for simulated annealing","author":"Huang M.","year":"1986","unstructured":"M. Huang , F. Romeo , and A. Sangiovanni-Vincentelli , \" An efficient general cooling schedule for simulated annealing ,\" in ICCAD , 1986 , pp. 381 -- 384 . M. Huang, F. Romeo, and A. Sangiovanni-Vincentelli, \"An efficient general cooling schedule for simulated annealing,\" in ICCAD, 1986, pp. 381--384.","journal-title":"ICCAD"},{"key":"e_1_3_2_1_19_1","first-page":"1","article-title":"Titan: Enabling large and complex benchmarks in academic CAD","author":"Murray K. E.","year":"2013","unstructured":"K. E. Murray , S. Whitty , S. Liu , J. Luu , and V. Betz , \" Titan: Enabling large and complex benchmarks in academic CAD ,\" in FPL , 2013 , pp. 1 -- 8 . K. E. Murray, S. Whitty, S. Liu, J. Luu, and V. Betz, \"Titan: Enabling large and complex benchmarks in academic CAD,\" in FPL, 2013, pp. 1--8.","journal-title":"FPL"}],"event":{"name":"DAC '17: The 54th Annual Design Automation Conference 2017","sponsor":["EDAC Electronic Design Automation Consortium","SIGDA ACM Special Interest Group on Design Automation","IEEE-CEDA","SIGBED ACM Special Interest Group on Embedded Systems"],"location":"Austin TX USA","acronym":"DAC '17"},"container-title":["Proceedings of the 54th Annual Design Automation Conference 2017"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3061639.3062198","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3061639.3062198","content-type":"application\/pdf","content-version":"vor","intended-application":"syndication"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3061639.3062198","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T03:36:34Z","timestamp":1750217794000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3061639.3062198"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,6,18]]},"references-count":19,"alternative-id":["10.1145\/3061639.3062198","10.1145\/3061639"],"URL":"https:\/\/doi.org\/10.1145\/3061639.3062198","relation":{},"subject":[],"published":{"date-parts":[[2017,6,18]]},"assertion":[{"value":"2017-06-18","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}