{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,25]],"date-time":"2026-04-25T21:52:08Z","timestamp":1777153928716,"version":"3.51.4"},"publisher-location":"New York, NY, USA","reference-count":21,"publisher":"ACM","license":[{"start":{"date-parts":[[2017,6,18]],"date-time":"2017-06-18T00:00:00Z","timestamp":1497744000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","award":["CCF-1217738"],"award-info":[{"award-number":["CCF-1217738"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2017,6,18]]},"DOI":"10.1145\/3061639.3062205","type":"proceedings-article","created":{"date-parts":[[2017,6,13]],"date-time":"2017-06-13T12:18:42Z","timestamp":1497356322000},"page":"1-6","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":29,"title":["ASSURE"],"prefix":"10.1145","author":[{"given":"Joydeep","family":"Rakshit","sequence":"first","affiliation":[{"name":"Department of Electrical and Computer Engineering, University of Pittsburgh, Pittsburgh"}]},{"given":"Kartik","family":"Mohanram","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, University of Pittsburgh, Pittsburgh"}]}],"member":"320","published-online":{"date-parts":[[2017,6,18]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555758"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/2463209.2488867"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/2694344.2694387"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/2897937.2898087"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/2872362.2872377"},{"key":"e_1_3_2_1_6_1","volume-title":"Intl. Symposium on Microarchitecture","author":"Suh G. E.","year":"2003","unstructured":"G. E. Suh memory integrity verification and encryption for secure processors,\" in Proc . Intl. Symposium on Microarchitecture , 2003 . G. E. Suh et al., \"Efficient memory integrity verification and encryption for secure processors,\" in Proc. Intl. Symposium on Microarchitecture, 2003."},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.44"},{"key":"e_1_3_2_1_8_1","volume-title":"Intl. Symposium on Microarchitecture","author":"Hilton A. D.","year":"2016","unstructured":"A. D. Hilton : Safe speculation for secure memory,\" in Proc . Intl. Symposium on Microarchitecture , 2016 . A. D. Hilton et al., \"PoisonIvy: Safe speculation for secure memory,\" in Proc. Intl. Symposium on Microarchitecture, 2016."},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/1186736.1186737"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2012.82"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/1065010.1065034"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/2024724.2024954"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"crossref","unstructured":"R. B. Lee \"Security basics for computer architects \" Synthesis Lectures on Computer Architecture vol. 8 no. 4 2013.   R. B. Lee \"Security basics for computer architects \" Synthesis Lectures on Computer Architecture vol. 8 no. 4 2013.","DOI":"10.2200\/S00512ED1V01Y201305CAC025"},{"key":"e_1_3_2_1_14_1","volume-title":"Handbook of applied cryptography","author":"Menezes A. J.","year":"1996","unstructured":"A. J. Menezes , Handbook of applied cryptography . CRC press , 1996 . A. J. Menezes et al., Handbook of applied cryptography. CRC press, 1996."},{"key":"e_1_3_2_1_15_1","volume-title":"Intl. Symposium on Computer Architecture","author":"Jiang L.","year":"2014","unstructured":"L. Jiang low power and reliable charge pump design for phase change memories,\" in Proc . Intl. Symposium on Computer Architecture , 2014 . L. Jiang et al., \"A low power and reliable charge pump design for phase change memories,\" in Proc. Intl. Symposium on Computer Architecture, 2014."},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2016.7446056"},{"key":"e_1_3_2_1_17_1","volume-title":"Intl. Conference on Computer Design","author":"Niu D.","year":"2013","unstructured":"D. Niu power multi-level cell resistive memory design with incomplete data mapping,\" in Proc . Intl. Conference on Computer Design , 2013 . D. Niu et al., \"Low power multi-level cell resistive memory design with incomplete data mapping,\" in Proc. Intl. Conference on Computer Design, 2013."},{"key":"e_1_3_2_1_18_1","volume-title":"Intl. Symposium on Circuits and Systems","author":"Yang B. D.","year":"2007","unstructured":"B. D. Yang low power phase change random access memory using a data-comparison write scheme,\" in Proc . Intl. Symposium on Circuits and Systems , 2007 . B. D. Yang et al., \"A low power phase change random access memory using a data-comparison write scheme,\" in Proc. Intl. Symposium on Circuits and Systems, 2007."},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669157"},{"key":"e_1_3_2_1_20_1","unstructured":"http:\/\/www.hpl.hp.com\/research\/cacti\/.  http:\/\/www.hpl.hp.com\/research\/cacti\/."},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/1055626.1055644"}],"event":{"name":"DAC '17: The 54th Annual Design Automation Conference 2017","location":"Austin TX USA","acronym":"DAC '17","sponsor":["EDAC Electronic Design Automation Consortium","SIGDA ACM Special Interest Group on Design Automation","IEEE-CEDA","SIGBED ACM Special Interest Group on Embedded Systems"]},"container-title":["Proceedings of the 54th Annual Design Automation Conference 2017"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3061639.3062205","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3061639.3062205","content-type":"application\/pdf","content-version":"vor","intended-application":"syndication"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3061639.3062205","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T03:36:34Z","timestamp":1750217794000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3061639.3062205"}},"subtitle":["Authentication Scheme for SecURE Energy Efficient Non-Volatile Memories"],"short-title":[],"issued":{"date-parts":[[2017,6,18]]},"references-count":21,"alternative-id":["10.1145\/3061639.3062205","10.1145\/3061639"],"URL":"https:\/\/doi.org\/10.1145\/3061639.3062205","relation":{},"subject":[],"published":{"date-parts":[[2017,6,18]]},"assertion":[{"value":"2017-06-18","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}