{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:08:36Z","timestamp":1750306116571,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":22,"publisher":"ACM","license":[{"start":{"date-parts":[[2017,6,18]],"date-time":"2017-06-18T00:00:00Z","timestamp":1497744000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2017,6,18]]},"DOI":"10.1145\/3061639.3062257","type":"proceedings-article","created":{"date-parts":[[2017,6,13]],"date-time":"2017-06-13T12:18:42Z","timestamp":1497356322000},"page":"1-6","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":10,"title":["HALWPE"],"prefix":"10.1145","author":[{"given":"Kenneth","family":"O'Neal","sequence":"first","affiliation":[{"name":"Department of Computer Science and Engineering, University of California, Riverside"}]},{"given":"Philip","family":"Brisk","sequence":"additional","affiliation":[{"name":"Department of Computer Science and Engineering, University of California, Riverside"}]},{"given":"Emily","family":"Shriver","sequence":"additional","affiliation":[{"name":"Strategic CAD Labs, Intel Corporation"}]},{"given":"Michael","family":"Kishinevsky","sequence":"additional","affiliation":[{"name":"Strategic CAD Labs, Intel Corporation"}]}],"member":"320","published-online":{"date-parts":[[2017,6,18]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/2830772.2830780"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICPP.2014.46"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2009.4919648"},{"key":"e_1_3_2_1_4_1","first-page":"231","volume-title":"Int. Symp. Perf. Analysis of Systems and Software, (ISPASS)","author":"del Barrio V.M.","year":"2006"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2011.6081376"},{"key":"e_1_3_2_1_6_1","first-page":"13","volume-title":"Symp. Perf. Analysis of Systems and Software (ISPASS)","author":"Gutierrez A.","year":"2014"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-0-387-21606-5"},{"key":"e_1_3_2_1_8_1","unstructured":"Intel Corporation \"The Compute Architecture of Intel Processor Graphics Gen7.5.\" {Online}. Available: https:\/\/goo.gl\/5HZ54v  Intel Corporation \"The Compute Architecture of Intel Processor Graphics Gen7.5.\" {Online}. Available: https:\/\/goo.gl\/5HZ54v"},{"key":"e_1_3_2_1_9_1","unstructured":"Intel Corporation \"The Compute Architecture of Intel Processor Graphics Gen8.\" {Online}. Available: https:\/\/goo.gl\/TnpAGc  Intel Corporation \"The Compute Architecture of Intel Processor Graphics Gen8.\" {Online}. Available: https:\/\/goo.gl\/TnpAGc"},{"key":"e_1_3_2_1_10_1","unstructured":"Intel Corporation \"The Compute Architecture of Intel Processor Graphics Gen9.\" {Online}. Available: https:\/\/goo.gl\/RMmUc6  Intel Corporation \"The Compute Architecture of Intel Processor Graphics Gen9.\" {Online}. Available: https:\/\/goo.gl\/RMmUc6"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/1168857.1168882"},{"key":"e_1_3_2_1_12_1","first-page":"257","volume-title":"Int. Conf. Parallel Architectures and Compilation Techniques (PACT)","author":"Jia W.","year":"2013"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/1168857.1168881"},{"volume-title":"Int. Symp. Perf. Anal. Systems and Software (ISPASS)","year":"2013","author":"Lee S.","key":"e_1_3_2_1_14_1"},{"volume-title":"ACM SOSP Workshop on Power Aware Computing and Systems (HotPower)","year":"2009","author":"Ma X.","key":"e_1_3_2_1_15_1"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICPP.2008.36"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2013.73"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/2370816.2370865"},{"key":"e_1_3_2_1_19_1","first-page":"564","volume-title":"Int. Symp. High Perf. Comp. Arch. (HPCA)","author":"Wu G.","year":"2015"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/NAS.2011.51"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/2897937.2897977"},{"key":"e_1_3_2_1_22_1","first-page":"52","volume-title":"Int. Conf. Embedded Computer Sys., Arch., Modeling and Simulation (SAMOS)","author":"Zheng X.","year":"2015"}],"event":{"name":"DAC '17: The 54th Annual Design Automation Conference 2017","sponsor":["EDAC Electronic Design Automation Consortium","SIGDA ACM Special Interest Group on Design Automation","IEEE-CEDA","SIGBED ACM Special Interest Group on Embedded Systems"],"location":"Austin TX USA","acronym":"DAC '17"},"container-title":["Proceedings of the 54th Annual Design Automation Conference 2017"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3061639.3062257","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3061639.3062257","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T03:36:35Z","timestamp":1750217795000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3061639.3062257"}},"subtitle":["Hardware-Assisted Light Weight Performance Estimation for GPUs"],"short-title":[],"issued":{"date-parts":[[2017,6,18]]},"references-count":22,"alternative-id":["10.1145\/3061639.3062257","10.1145\/3061639"],"URL":"https:\/\/doi.org\/10.1145\/3061639.3062257","relation":{},"subject":[],"published":{"date-parts":[[2017,6,18]]},"assertion":[{"value":"2017-06-18","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}