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Code Optim."],"published-print":{"date-parts":[[2017,6,30]]},"abstract":"<jats:p>Recently, processors have begun integrating 3D stacked DRAMs with the cores on the same package, and there have been several approaches to effectively utilizing the on-package DRAMs as caches. This article presents an approach that combines the previous approaches in a synergistic way by devising a module called the dirty-block tracker to maintain the dirtiness of each block in a dirty region. The approach avoids unnecessary tag checking for a write operation if the corresponding block in the cache is not dirty. Our simulation results show that the proposed technique achieves a 10.3% performance improvement on average over the state-of-the-art DRAM cache technique.<\/jats:p>","DOI":"10.1145\/3068460","type":"journal-article","created":{"date-parts":[[2017,5,10]],"date-time":"2017-05-10T18:08:53Z","timestamp":1494439733000},"page":"1-25","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":2,"title":["Dirty-Block Tracking in a Direct-Mapped DRAM Cache with Self-Balancing Dispatch"],"prefix":"10.1145","volume":"14","author":[{"given":"Dongwoo","family":"Lee","sequence":"first","affiliation":[{"name":"Seoul National University, Seoul"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sangheon","family":"Lee","sequence":"additional","affiliation":[{"name":"Samsung Advanced Institute of Technology, Suwon, Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Soojung","family":"Ryu","sequence":"additional","affiliation":[{"name":"Samsung Advanced Institute of Technology, Suwon, Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kiyoung","family":"Choi","sequence":"additional","affiliation":[{"name":"Seoul National University, Seoul"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2017,5,10]]},"reference":[{"key":"e_1_2_2_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2013.6557148"},{"volume-title":"Proceedings of the Design, Automation 8 Test in Europe Conference 8 Exhibition (DATE\u201912)","author":"Chen Ke","key":"e_1_2_2_2_1"},{"key":"e_1_2_2_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2014.63"},{"key":"e_1_2_2_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/2749469.2750387"},{"key":"e_1_2_2_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2014.36"},{"key":"e_1_2_2_6_1","first-page":"1","article-title":"Simpoint 3.0: Faster and more flexible program phase analysis","volume":"7","author":"Hamerly Greg","year":"2005","journal-title":"Journal of Instruction Level Parallelism"},{"key":"e_1_2_2_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/1186736.1186737"},{"key":"e_1_2_2_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/2628071.2628089"},{"key":"e_1_2_2_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2012.6242474"},{"key":"e_1_2_2_10_1","unstructured":"High Bandwidth Memory JEDEC. 2013. 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