{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,8,22]],"date-time":"2026-08-22T07:32:56Z","timestamp":1787383976633,"version":"build-2736575974"},"publisher-location":"New York, NY, USA","reference-count":43,"publisher":"ACM","license":[{"start":{"date-parts":[[2017,5,15]],"date-time":"2017-05-15T00:00:00Z","timestamp":1494806400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","award":["IIS-1247693"],"award-info":[{"award-number":["IIS-1247693"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000181","name":"Air Force Office of Scientific Research","doi-asserted-by":"publisher","award":["FA9550-12-1-0442"],"award-info":[{"award-number":["FA9550-12-1-0442"]}],"id":[{"id":"10.13039\/100000181","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2017,5,15]]},"DOI":"10.1145\/3075564.3075583","type":"proceedings-article","created":{"date-parts":[[2017,6,7]],"date-time":"2017-06-07T12:47:29Z","timestamp":1496839649000},"page":"107-116","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":14,"title":["GPU-UniCache"],"prefix":"10.1145","author":[{"given":"Kaixi","family":"Hou","sequence":"first","affiliation":[{"name":"Department of Computer Science, Virginia Tech, Blacksburg, VA, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Hao","family":"Wang","sequence":"additional","affiliation":[{"name":"Department of Computer Science, Virginia Tech, Blacksburg, VA, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Wu-chun","family":"Feng","sequence":"additional","affiliation":[{"name":"Department of Computer Science, Virginia Tech, Blacksburg, VA, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2017,5,15]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"AMD. 2016. Graphics Core Next Architecture Generation 3 Reference Guide. (2016). Revision1.1.  AMD. 2016. Graphics Core Next Architecture Generation 3 Reference Guide. (2016). Revision1.1."},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/2925426.2926259"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2011.70"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"crossref","unstructured":"X. Cui T. RW Scogland B. R de Supinski and W.-c. Feng. 2016. Directive-Based Pipelining Extension for OpenMP. In IEEE Int'l Conf. Cluster Computing (CLUSTER).  X. Cui T. RW Scogland B. R de Supinski and W.-c. Feng. 2016. Directive-Based Pipelining Extension for OpenMP. In IEEE Int'l Conf. Cluster Computing (CLUSTER).","DOI":"10.1109\/CLUSTER.2016.53"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/1735688.1735702"},{"key":"e_1_3_2_1_6_1","unstructured":"K. Datta S. Williams V. Volkov J. Carter L. Oliker J. Shalf and K. Yelick. 2009. Auto-tuning the 27-point Stencil for Multicore. In Int'l Workshop on Automatic Performance Tuning (iWAPT).  K. Datta S. Williams V. Volkov J. Carter L. Oliker J. Shalf and K. Yelick. 2009. Auto-tuning the 27-point Stencil for Multicore. In Int'l Workshop on Automatic Performance Tuning (iWAPT)."},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"crossref","unstructured":"T. L. Falch and A. C. Elster. 2014. Register Caching for Stencil Computations on GPUs. In Int'l Symp. on Symbolic and Numeric Algorithms for Sci. Comp. (SYNASC).  T. L. Falch and A. C. Elster. 2014. Register Caching for Stencil Computations on GPUs. In Int'l Symp. on Symbolic and Numeric Algorithms for Sci. Comp. (SYNASC).","DOI":"10.1109\/SYNASC.2014.70"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/2464996.2467268"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/2304576.2304619"},{"key":"e_1_3_2_1_10_1","volume-title":"Workshops (IPDPSW).","author":"Hou K."},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/3079079.3079105"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/2751205.2751247"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"crossref","unstructured":"K. Hou H. Wang and W.-c. Feng. 2016. AAlign: A SIMD Framework for Pairwise Sequence Alignment on x86-Based Multi-and Many-Core Processors. In IEEE Int'l Parallel & Distributed Processing Symp. (IPDPS).  K. Hou H. Wang and W.-c. Feng. 2016. AAlign: A SIMD Framework for Pairwise Sequence Alignment on x86-Based Multi-and Many-Core Processors. In IEEE Int'l Parallel & Distributed Processing Symp. (IPDPS).","DOI":"10.1109\/IPDPS.2016.115"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"crossref","unstructured":"K. Hou Y. Zhao J. Huang and L. Zhang. 2011. Performance Evaluation of the Three-Dimensional Finite-Difference Time-Do main(EDTD) Method on Fermi Architecture GPUs. In Int'l Conf. on Algorithms and Architectures for Parallel Processing (ICA3PP). Springer Berlin Heidelberg.   K. Hou Y. Zhao J. Huang and L. Zhang. 2011. Performance Evaluation of the Three-Dimensional Finite-Difference Time-Do main(EDTD) Method on Fermi Architecture GPUs. In Int'l Conf. on Algorithms and Architectures for Parallel Processing (ICA3PP). Springer Berlin Heidelberg.","DOI":"10.1007\/978-3-642-24650-0_40"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"crossref","unstructured":"Q. Jia and H. Zhou. 2016. Tuning Stencil codes in OpenCL for FPGAs. In IEEE Int'l Conf. on Computer Design (ICCD).  Q. Jia and H. Zhou. 2016. Tuning Stencil codes in OpenCL for FPGAs. In IEEE Int'l Conf. on Computer Design (ICCD).","DOI":"10.1109\/ICCD.2016.7753287"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/1250734.1250761"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-43659-3_45"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/2751205.2751209"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.jpdc.2015.06.010"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/2628071.2628121"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/2751205.2751214"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/2503210.2503268"},{"key":"e_1_3_2_1_23_1","unstructured":"N. Maruyama and T. Aoki. 2014. Optimizing stencil computations for NVIDIA Kepler GPUs. In Int'l Workshop on High-Performance Stencil Comp. (HiStencils).  N. Maruyama and T. Aoki. 2014. Optimizing stencil computations for NVIDIA Kepler GPUs. In Int'l Workshop on High-Performance Stencil Comp. (HiStencils)."},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1145\/2063384.2063398"},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2014.67"},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1109\/SC.2010.2"},{"key":"e_1_3_2_1_27_1","unstructured":"NVIDIA. 2014. NVIDIA's Next Generation CUDA Compute Architecture Kepler GK110. (2014). v1.0.  NVIDIA. 2014. NVIDIA's Next Generation CUDA Compute Architecture Kepler GK110. (2014). v1.0."},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPSW.2012.228"},{"key":"e_1_3_2_1_29_1","volume-title":"Polybench: The polyhedral benchmark suite.","author":"Pouchet L.-N.","year":"2015"},{"key":"e_1_3_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1145\/2967938.2967967"},{"key":"e_1_3_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1145\/2884045.2884047"},{"key":"e_1_3_2_1_32_1","volume-title":"Parboil: A revised benchmark suite for scientific and commercial throughput computing","author":"Stratton J. A","year":"2012"},{"key":"e_1_3_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1145\/1989493.1989508"},{"key":"e_1_3_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1145\/1995896.1995932"},{"key":"e_1_3_2_1_35_1","volume-title":"Optimized Three-dimensional Stencil Computation on Fermi and Kepler GPUs. In High Performance Extreme Computing Conf. (HPEC).","author":"Vizitiu A."},{"key":"e_1_3_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1145\/2749246.2749255"},{"key":"e_1_3_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1145\/2925426.2926291"},{"key":"e_1_3_2_1_38_1","doi-asserted-by":"crossref","unstructured":"H. Wang S. Potluri D. Bureddy C. Rosales and D. K. Panda. 2014. GPU-Aware MPI on RDMA-Enabled Clusters: Design Implementation and Evaluation. IEEE Transactions on Parallel and Distributed Systems (TPDS) (2014).  H. Wang S. Potluri D. Bureddy C. Rosales and D. K. Panda. 2014. GPU-Aware MPI on RDMA-Enabled Clusters: Design Implementation and Evaluation. IEEE Transactions on Parallel and Distributed Systems (TPDS) (2014).","DOI":"10.1109\/TPDS.2013.222"},{"key":"e_1_3_2_1_39_1","doi-asserted-by":"publisher","DOI":"10.1145\/1498765.1498785"},{"key":"e_1_3_2_1_40_1","doi-asserted-by":"publisher","DOI":"10.1145\/2482767.2482791"},{"key":"e_1_3_2_1_41_1","unstructured":"F. Zhang. 2014. Automatic Loop Tuning and Memory Management for Stencil Computations. (2014). http:\/\/scholarcommons.sc.edu\/etd\/3012 (Doctoral Dissertation).  F. Zhang. 2014. Automatic Loop Tuning and Memory Management for Stencil Computations. (2014). http:\/\/scholarcommons.sc.edu\/etd\/3012 (Doctoral Dissertation)."},{"key":"e_1_3_2_1_42_1","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2014.36"},{"key":"e_1_3_2_1_43_1","doi-asserted-by":"publisher","DOI":"10.1145\/2259016.2259037"}],"event":{"name":"CF '17: Computing Frontiers Conference","location":"Siena Italy","acronym":"CF '17","sponsor":["SIGMICRO ACM Special Interest Group on Microarchitectural Research and Processing"]},"container-title":["Proceedings of the Computing Frontiers Conference"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3075564.3075583","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3075564.3075583","content-type":"application\/pdf","content-version":"vor","intended-application":"syndication"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3075564.3075583","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T03:03:42Z","timestamp":1750215822000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3075564.3075583"}},"subtitle":["Automatic Code Generation of Spatial Blocking for Stencils on GPUs"],"short-title":[],"issued":{"date-parts":[[2017,5,15]]},"references-count":43,"alternative-id":["10.1145\/3075564.3075583","10.1145\/3075564"],"URL":"https:\/\/doi.org\/10.1145\/3075564.3075583","relation":{},"subject":[],"published":{"date-parts":[[2017,5,15]]},"assertion":[{"value":"2017-05-15","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}