{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,20]],"date-time":"2026-02-20T18:57:29Z","timestamp":1771613849474,"version":"3.50.1"},"publisher-location":"New York, NY, USA","reference-count":51,"publisher":"ACM","license":[{"start":{"date-parts":[[2017,6,14]],"date-time":"2017-06-14T00:00:00Z","timestamp":1497398400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2017,6,14]]},"DOI":"10.1145\/3079079.3079090","type":"proceedings-article","created":{"date-parts":[[2017,5,31]],"date-time":"2017-05-31T19:31:40Z","timestamp":1496259100000},"page":"1-11","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":10,"title":["Carpool"],"prefix":"10.1145","author":[{"given":"Xiyue","family":"Xiang","sequence":"first","affiliation":[{"name":"University of Louisiana at Lafayette"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Wentao","family":"Shi","sequence":"additional","affiliation":[{"name":"Louisiana State University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Saugata","family":"Ghose","sequence":"additional","affiliation":[{"name":"Carnegie Mellon University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Lu","family":"Peng","sequence":"additional","affiliation":[{"name":"Louisiana State University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Onur","family":"Mutlu","sequence":"additional","affiliation":[{"name":"ETH Z\u00fcrich and Carnegie Mellon University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Nian-Feng","family":"Tzeng","sequence":"additional","affiliation":[{"name":"University of Louisiana at Lafayette"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2017,6,14]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/1250662.1250678"},{"key":"e_1_3_2_1_2_1","volume-title":"MRR: Enabling Fully Adaptive Multicast Routing for CMP Inter-connect Networks,\" in HPCA","author":"Abad P.","year":"2009","unstructured":"P. Abad , \" MRR: Enabling Fully Adaptive Multicast Routing for CMP Inter-connect Networks,\" in HPCA , 2009 . P. Abad et al., \"MRR: Enabling Fully Adaptive Multicast Routing for CMP Inter-connect Networks,\" in HPCA, 2009."},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/SBAC-PAD.2014.31"},{"key":"e_1_3_2_1_4_1","volume-title":"A Case for Hierarchical Rings with Deflection Routing: An Energy-Efficient On-Chip Communication Substrate,\" PARCO","author":"Ausavarungnirun R.","year":"2016","unstructured":"R. Ausavarungnirun , \" A Case for Hierarchical Rings with Deflection Routing: An Energy-Efficient On-Chip Communication Substrate,\" PARCO , 2016 . R. Ausavarungnirun et al., \"A Case for Hierarchical Rings with Deflection Routing: An Energy-Efficient On-Chip Communication Substrate,\" PARCO, 2016."},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"crossref","unstructured":"P. Baran \"On Distributed Communications Networks \" TCOM 1964.  P. Baran \"On Distributed Communications Networks \" TCOM 1964.","DOI":"10.7249\/RM3766"},{"key":"e_1_3_2_1_6_1","unstructured":"Cadence Design Systems Inc. \"SOC Encounter User Guide \" http:\/\/www.cadence.com\/products\/di\/firstencounter\/.  Cadence Design Systems Inc. \"SOC Encounter User Guide \" http:\/\/www.cadence.com\/products\/di\/firstencounter\/."},{"key":"e_1_3_2_1_7_1","volume-title":"Comparative Evaluation of FPGA and ASIC Implementations of Bufferless and Buffered Routing Algorithms for On-Chip Networks,\" in ISQED","author":"Cai Y.","year":"2015","unstructured":"Y. Cai , \" Comparative Evaluation of FPGA and ASIC Implementations of Bufferless and Buffered Routing Algorithms for On-Chip Networks,\" in ISQED , 2015 . Y. Cai et al., \"Comparative Evaluation of FPGA and ASIC Implementations of Bufferless and Buffered Routing Algorithms for On-Chip Networks,\" in ISQED, 2015."},{"key":"e_1_3_2_1_8_1","volume-title":"Evaluation of a Multithreaded Architecture for Cellular Computing,\" in HPCA","author":"Castanos J. G.","year":"2002","unstructured":"J. G. Castanos , \" Evaluation of a Multithreaded Architecture for Cellular Computing,\" in HPCA , 2002 . J. G. Castanos et al., \"Evaluation of a Multithreaded Architecture for Cellular Computing,\" in HPCA, 2002."},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/SBAC-PAD.2012.44"},{"key":"e_1_3_2_1_10_1","volume-title":"Multi-Address Encoding for Multicast,\" in PCRCW","author":"Chiang C.-M.","year":"1994","unstructured":"C.-M. Chiang and L. M. Ni , \" Multi-Address Encoding for Multicast,\" in PCRCW , 1994 . C.-M. Chiang and L. M. Ni, \"Multi-Address Encoding for Multicast,\" in PCRCW, 1994."},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/71.219761"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"crossref","DOI":"10.21236\/ADA442968","volume-title":"The Torus Routing Chip,\" Distributed Computing","author":"Dally W. J.","year":"1986","unstructured":"W. J. Dally and C. L. Seitz , \" The Torus Routing Chip,\" Distributed Computing , 1986 . W. J. Dally and C. L. Seitz, \"The Torus Routing Chip,\" Distributed Computing, 1986."},{"key":"e_1_3_2_1_14_1","volume-title":"Principles and Practices of Interconnection Networks","author":"Dally W. J.","year":"2003","unstructured":"W. J. Dally and B. Towles , Principles and Practices of Interconnection Networks . Morgan Kaufmann Publishers , 2003 . W. J. Dally and B. Towles, Principles and Practices of Interconnection Networks. Morgan Kaufmann Publishers, 2003."},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/2897937.2898075"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/2000064.2000081"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/1736020.1736058"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.12"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2012.8"},{"key":"e_1_3_2_1_20_1","volume-title":"CHIPPER: A Low-Complexity Bufferless Deflection Router,\" in HPCA","author":"Fallin C.","year":"2011","unstructured":"C. Fallin , \" CHIPPER: A Low-Complexity Bufferless Deflection Router,\" in HPCA , 2011 . C. Fallin et al., \"CHIPPER: A Low-Complexity Bufferless Deflection Router,\" in HPCA, 2011."},{"key":"e_1_3_2_1_21_1","volume-title":"Bufferless and Minimally-Buffered Deflection Routing,\" in Routing Algorithms in Networks-on-Chip","author":"Fallin C.","year":"2014","unstructured":"C. Fallin , \" Bufferless and Minimally-Buffered Deflection Routing,\" in Routing Algorithms in Networks-on-Chip . Springer , 2014 . C. Fallin et al., \"Bufferless and Minimally-Buffered Deflection Routing,\" in Routing Algorithms in Networks-on-Chip. Springer, 2014."},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/2786572.2786591"},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2005.99"},{"key":"e_1_3_2_1_24_1","volume-title":"Regional Congestion Awareness for Load Balance in Networks-on-Chip,\" in HPCA","author":"Gratz P.","year":"2008","unstructured":"P. Gratz , \" Regional Congestion Awareness for Load Balance in Networks-on-Chip,\" in HPCA , 2008 . P. Gratz et al., \"Regional Congestion Awareness for Load Balance in Networks-on-Chip,\" in HPCA, 2008."},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669144"},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2007.346209"},{"key":"e_1_3_2_1_27_1","volume-title":"Virtual Cut-Through: A New Computer Communication Switching Technique,\" Computer Networks","author":"Kermani P.","year":"1979","unstructured":"P. Kermani and L. Kleinrock , \" Virtual Cut-Through: A New Computer Communication Switching Technique,\" Computer Networks , 1979 . P. Kermani and L. Kleinrock, \"Virtual Cut-Through: A New Computer Communication Switching Technique,\" Computer Networks, 1979."},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1109\/L-CA.2012.22"},{"key":"e_1_3_2_1_29_1","volume-title":"Extending Bufferless On-Chip Networks to High-Throughput Workloads,\" in NOCS","author":"Kim H.","year":"2014","unstructured":"H. Kim , \" Extending Bufferless On-Chip Networks to High-Throughput Workloads,\" in NOCS , 2014 . H. Kim et al., \"Extending Bufferless On-Chip Networks to High-Throughput Workloads,\" in NOCS, 2014."},{"key":"e_1_3_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1145\/1065579.1065726"},{"key":"e_1_3_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1145\/2155620.2155630"},{"key":"e_1_3_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2006.31"},{"key":"e_1_3_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555781"},{"key":"e_1_3_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.50"},{"key":"e_1_3_2_1_35_1","unstructured":"\"NOCulator \" https:\/\/github.com\/CMU-SAFARI\/NOCulator\/.  \"NOCulator \" https:\/\/github.com\/CMU-SAFARI\/NOCulator\/."},{"key":"e_1_3_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1145\/2342356.2342436"},{"key":"e_1_3_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1145\/1868447.1868459"},{"key":"e_1_3_2_1_38_1","unstructured":"Oklahoma State Univ. \"FreePDK Standard Cell Libraries \" https:\/\/vlsiarch.ecen.okstate.edu\/flows\/.  Oklahoma State Univ. \"FreePDK Standard Cell Libraries \" https:\/\/vlsiarch.ecen.okstate.edu\/flows\/."},{"key":"e_1_3_2_1_39_1","volume-title":"A 1024-Core 70 GFLOP\/W Floating Point Manycore Microprocessor,\" in HPEC","author":"Olofsson A.","year":"2011","unstructured":"A. Olofsson , \" A 1024-Core 70 GFLOP\/W Floating Point Manycore Microprocessor,\" in HPEC , 2011 . A. Olofsson et al., \"A 1024-Core 70 GFLOP\/W Floating Point Manycore Microprocessor,\" in HPEC, 2011."},{"key":"e_1_3_2_1_40_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2008.4771805"},{"key":"e_1_3_2_1_41_1","doi-asserted-by":"publisher","DOI":"10.1145\/1403375.1403714"},{"key":"e_1_3_2_1_42_1","doi-asserted-by":"publisher","DOI":"10.1145\/859618.859641"},{"key":"e_1_3_2_1_43_1","doi-asserted-by":"crossref","unstructured":"B. Smith \"Architecture and Applications of the HEP Multiprocessor Computer System \" SPIE 1982.  B. Smith \"Architecture and Applications of the HEP Multiprocessor Computer System \" SPIE 1982.","DOI":"10.1117\/12.932535"},{"key":"e_1_3_2_1_44_1","doi-asserted-by":"publisher","DOI":"10.1145\/331532.331548"},{"key":"e_1_3_2_1_45_1","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2012.31"},{"key":"e_1_3_2_1_46_1","volume-title":"Self-Tuned Congestion Control for Multiprocessor Networks,\" in HPCA","author":"Thottethodi M.","year":"2001","unstructured":"M. Thottethodi , \" Self-Tuned Congestion Control for Multiprocessor Networks,\" in HPCA , 2001 . M. Thottethodi et al., \"Self-Tuned Congestion Control for Multiprocessor Networks,\" in HPCA, 2001."},{"key":"e_1_3_2_1_47_1","unstructured":"J. S. Turner \"An Optimal Nonblocking Multicast Virtual Circuit Switch \" in INFOCOM 1994.  J. S. Turner \"An Optimal Nonblocking Multicast Virtual Circuit Switch \" in INFOCOM 1994."},{"key":"e_1_3_2_1_48_1","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2009.5071446"},{"key":"e_1_3_2_1_49_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2010.15"},{"key":"e_1_3_2_1_50_1","volume-title":"A Model for Application Slowdown Estimation in On-Chip Networks and Its Use for Improving System Fairness and Performance,\" in ICCD","author":"Xiang X.","year":"2016","unstructured":"X. Xiang , \" A Model for Application Slowdown Estimation in On-Chip Networks and Its Use for Improving System Fairness and Performance,\" in ICCD , 2016 . X. Xiang et al., \"A Model for Application Slowdown Estimation in On-Chip Networks and Its Use for Improving System Fairness and Performance,\" in ICCD, 2016."},{"key":"e_1_3_2_1_51_1","doi-asserted-by":"crossref","unstructured":"X. Xiang and N.-F. Tzeng \"Deflection Containment for Bufferless Network-on-Chips \" in IPDPS 2016.  X. Xiang and N.-F. Tzeng \"Deflection Containment for Bufferless Network-on-Chips \" in IPDPS 2016.","DOI":"10.1109\/IPDPS.2016.17"},{"key":"e_1_3_2_1_52_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1987.1676921"}],"event":{"name":"ICS '17: 2017 International Conference on Supercomputing","location":"Chicago Illinois","acronym":"ICS '17","sponsor":["SIGARCH ACM Special Interest Group on Computer Architecture"]},"container-title":["Proceedings of the International Conference on Supercomputing"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3079079.3079090","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3079079.3079090","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T03:03:25Z","timestamp":1750215805000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3079079.3079090"}},"subtitle":["a bufferless on-chip network supporting adaptive multicast and hotspot alleviation"],"short-title":[],"issued":{"date-parts":[[2017,6,14]]},"references-count":51,"alternative-id":["10.1145\/3079079.3079090","10.1145\/3079079"],"URL":"https:\/\/doi.org\/10.1145\/3079079.3079090","relation":{},"subject":[],"published":{"date-parts":[[2017,6,14]]},"assertion":[{"value":"2017-06-14","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}