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Syst."],"published-print":{"date-parts":[[2017,9,30]]},"abstract":"<jats:p>Field-programmable gate arrays (FPGA) are an increasingly attractive alternative to traditional microprocessor-based computing architectures in extreme-computing domains, such as aerospace and supercomputing. FPGAs offer several resource types that offer different tradeoffs between speed, power, and area, which make FPGAs highly flexible for varying application computational requirements. However, since an application\u2019s computational operations can map to different resource types, a major challenge in leveraging resource-diverse FPGAs is determining the optimal distribution of these operations across the device\u2019s available resources for varying FPGA devices, resulting in an extremely large design space. In order to facilitate fast design-space exploration, this article presents a method based on linear programming (LP) that determines the optimal operation distribution for a particular device and application with respect to performance, power, or dependability metrics. Our LP method is an effective tool for exploring early designs by quickly analyzing thousands of FPGAs to determine the best FPGA devices and operation distributions, which significantly reduces design time. We demonstrate our LP method\u2019s effectiveness with two case studies involving dot-product and distance-calculation kernels on a range of Virtex-5 FPGAs. Results show that our LP method selects optimal distributions of operations to within an average of 4% of actual values.<\/jats:p>","DOI":"10.1145\/3079756","type":"journal-article","created":{"date-parts":[[2017,6,30]],"date-time":"2017-06-30T12:36:19Z","timestamp":1498826179000},"page":"1-23","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":3,"title":["Optimizing FPGA Performance, Power, and Dependability with Linear Programming"],"prefix":"10.1145","volume":"10","author":[{"given":"Nicholas","family":"Wulf","sequence":"first","affiliation":[{"name":"NSF Center for High-Performance Reconfigurable Computing (CHREC), University of Florida"}]},{"given":"Alan D.","family":"George","sequence":"additional","affiliation":[{"name":"NSF Center for High-Performance Reconfigurable Computing (CHREC), University of Florida"}]},{"given":"Ann","family":"Gordon-Ross","sequence":"additional","affiliation":[{"name":"NSF Center for High-Performance Reconfigurable Computing (CHREC), University of Florida"}]}],"member":"320","published-online":{"date-parts":[[2017,6,29]]},"reference":[{"key":"e_1_2_1_1_1","volume-title":"Proceedings of the Twelfth International Conference on VLSI Design. 434--439","author":"Agrawal V. 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