{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,10]],"date-time":"2026-03-10T04:32:51Z","timestamp":1773117171814,"version":"3.50.1"},"publisher-location":"New York, NY, USA","reference-count":54,"publisher":"ACM","license":[{"start":{"date-parts":[[2017,6,24]],"date-time":"2017-06-24T00:00:00Z","timestamp":1498262400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","award":["CNS-1302260, CCF-1438992, CCF-1533885, CCF- 1617824"],"award-info":[{"award-number":["CNS-1302260, CCF-1438992, CCF-1533885, CCF- 1617824"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2017,6,24]]},"DOI":"10.1145\/3079856.3080216","type":"proceedings-article","created":{"date-parts":[[2017,6,15]],"date-time":"2017-06-15T15:40:01Z","timestamp":1497541201000},"page":"375-388","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":24,"title":["LogCA"],"prefix":"10.1145","author":[{"given":"Muhammad Shoaib Bin","family":"Altaf","sequence":"first","affiliation":[{"name":"AMD Research Advanced, Micro Devices, Inc."}]},{"given":"David A.","family":"Wood","sequence":"additional","affiliation":[{"name":"Computer Sciences Department, University of Wisconsin-Madison"}]}],"member":"320","published-online":{"date-parts":[[2017,6,24]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"Advanced Micro Devices 2016. APP SDK - A Complete Development Platform. Advanced Micro Devices. http:\/\/developer.amd.com\/tools-and-sdks\/opencl-zone\/amd-accelerated-parallel-processing-app-sdk\/."},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/1465482.1465560"},{"key":"e_1_3_2_1_3_1","unstructured":"Dan Anderson. 2012. How to tell if SPARC T4 crypto is being used? https:\/\/blogs.oracle.com\/DanX\/entry\/how_to_tell_if_sparc."},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/1562764.1562783"},{"key":"e_1_3_2_1_5_1","first-page":"1","article-title":"Cache Calculus: Modeling Caches through Differential Equations","volume":"99","author":"Beckmann Nathan","year":"2016","unstructured":"Nathan Beckmann and Daniel Sanchez. 2016. Cache Calculus: Modeling Caches through Differential Equations. Computer Architecture Letters PP, 99 (2016), 1. http:\/\/ieeexplore.ieee.org\/lpdocs\/epic03\/wrapper.htm?arnumber=7366753$\\delimiter\"026E30F$npapers3:\/\/publication\/doi\/10.1109\/LCA.2015.2512873","journal-title":"Computer Architecture Letters PP"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1147\/JRD.2010.2059721"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2010.36"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.5555\/2840819.2840873"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/155332.155333"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1155\/2013\/428078"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/SAAHPC.2011.29"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/2000064.2000108"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1147\/JRD.2009.2036980"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.5555\/2014698.2014884"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1815968"},{"key":"e_1_3_2_1_17_1","volume-title":"ISCA Workshop on Modeling, Benchmarking, and Simulations (MoBS).","author":"Hempstead Mark","year":"2009","unstructured":"Mark Hempstead, Gu-Yeon Wei, and David Brooks. 2009. Navigo: An early-stage model to study power-constrained architectures and specialization. In ISCA Workshop on Modeling, Benchmarking, and Simulations (MoBS)."},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.5555\/1200662"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2008.209"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555775"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1815998"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-32820-6_90"},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1145\/2540708.2540748"},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1007\/s11036-012-0368-0"},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1145\/2751205.2751231"},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1109\/L-CA.2013.17"},{"key":"e_1_3_2_1_27_1","volume-title":"Building intuition","author":"Little John D C","unstructured":"John D C Little and Stephen C Graves. 2008. Little's law. In Building intuition. Springer, 81--100."},{"key":"e_1_3_2_1_28_1","first-page":"1","article-title":"A Survey of Performance Modeling and Simulation Techniques for Accelerator-Based Computing. Parallel and Distributed Systems","volume":"26","author":"Lopez-Novoa U","year":"2015","unstructured":"U Lopez-Novoa, A Mendiburu, and J Miguel-Alonso. 2015. A Survey of Performance Modeling and Simulation Techniques for Accelerator-Based Computing. Parallel and Distributed Systems, IEEE Transactions on 26, 1 (jan 2015), 272--281.","journal-title":"IEEE Transactions on"},{"key":"e_1_3_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1177\/1094342012468180"},{"key":"e_1_3_2_1_30_1","volume-title":"Advanced Encryption Standard (AES)","author":"National Institute of Standards and Technology 2001.","unstructured":"National Institute of Standards and Technology 2001. Advanced Encryption Standard (AES). National Institute of Standards and Technology."},{"key":"e_1_3_2_1_31_1","volume-title":"Secure Hash Standard","author":"National Institute of Standards and Technology 2008.","unstructured":"National Institute of Standards and Technology 2008. Secure Hash Standard. National Institute of Standards and Technology. http:\/\/csrc.nist.gov\/publications\/fips\/fips180-3\/fips180-3_final.pdf."},{"key":"e_1_3_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1109\/L-CA.2012.9"},{"key":"e_1_3_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1145\/2212908.2212937"},{"key":"e_1_3_2_1_34_1","volume-title":"Cryptography and SSL\/TLS Toolkit","author":"Software SSL","unstructured":"OpenSSL Software Foundation 2015. OpenSSL, Cryptography and SSL\/TLS Toolkit. OpenSSL Software Foundation. https:\/\/openssl.org."},{"key":"e_1_3_2_1_35_1","volume-title":"21st Hot Chip Symposium. http:\/\/www.hotchips.org\/wp-content\/uploads\/hc","author":"Patel Sanjay","year":"2009","unstructured":"Sanjay Patel. 2009. Sun's Next-Generation Multithreaded Processor: Rainbow Falls. In 21st Hot Chip Symposium. http:\/\/www.hotchips.org\/wp-content\/uploads\/hc"},{"key":"e_1_3_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2008.50"},{"key":"e_1_3_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1109\/HOTCHIPS.2014.7478832"},{"key":"e_1_3_2_1_38_1","doi-asserted-by":"crossref","unstructured":"Phil Rogers. 2013. Heterogeneous system architecture overview. In Hot Chips.","DOI":"10.1109\/HOTCHIPS.2013.7478286"},{"key":"e_1_3_2_1_39_1","doi-asserted-by":"publisher","DOI":"10.1145\/1621960.1621962"},{"key":"e_1_3_2_1_40_1","doi-asserted-by":"publisher","DOI":"10.1109\/ASSCC.2007.4425786"},{"key":"e_1_3_2_1_41_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2012.1"},{"key":"e_1_3_2_1_42_1","doi-asserted-by":"publisher","DOI":"10.5555\/2665671.2665689"},{"key":"e_1_3_2_1_43_1","unstructured":"Soekris Engineering 2016. vpn 1401 for Std. PCI-sockets. Soekris Engineering. http:\/\/soekris.com\/products\/vpn-1401.html."},{"key":"e_1_3_2_1_44_1","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2013.73"},{"key":"e_1_3_2_1_45_1","doi-asserted-by":"publisher","DOI":"10.1109\/HOTCHIPS.2013.7478303"},{"key":"e_1_3_2_1_47_1","doi-asserted-by":"publisher","DOI":"10.1007\/s11227-014-1102-4"},{"key":"e_1_3_2_1_48_1","doi-asserted-by":"publisher","DOI":"10.5555\/2588259"},{"key":"e_1_3_2_1_49_1","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228567"},{"key":"e_1_3_2_1_50_1","doi-asserted-by":"publisher","unstructured":"G Venkatesh J Sampson N Goulding S Garcia V Bryksin J Lugo-Martinez S Swanson and M B Taylor. 2010. Conservation cores: Reducing the energy of mature computations. In s and Operating Systems - ASPLOS. 205--218. 10.1145\/1735970.1736044","DOI":"10.1145\/1735970.1736044"},{"key":"e_1_3_2_1_51_1","doi-asserted-by":"publisher","DOI":"10.1145\/2155620.2155640"},{"key":"e_1_3_2_1_52_1","doi-asserted-by":"publisher","DOI":"10.1109\/GreenCom-CPSCom.2010.102"},{"key":"e_1_3_2_1_53_1","unstructured":"Eric W. Weisstein. 2015. Newton's Method. From MathWorld -- A Wolfram Web Resource. http:\/\/mathworld.wolfram.com\/NewtonsMethod.html."},{"key":"e_1_3_2_1_54_1","doi-asserted-by":"publisher","DOI":"10.1145\/1498765.1498785"},{"key":"e_1_3_2_1_55_1","doi-asserted-by":"publisher","DOI":"10.1145\/2541940.2541961"},{"key":"e_1_3_2_1_57_1","doi-asserted-by":"publisher","DOI":"10.5555\/2014698.2014875"}],"event":{"name":"ISCA '17: The 44th Annual International Symposium on Computer Architecture","location":"Toronto ON Canada","acronym":"ISCA '17","sponsor":["IEEE IEEE Computer Society Technical Committee on Design Automation","SIGARCH ACM Special Interest Group on Computer Architecture"]},"container-title":["Proceedings of the 44th Annual International Symposium on Computer Architecture"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3079856.3080216","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3079856.3080216","content-type":"application\/pdf","content-version":"vor","intended-application":"syndication"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3079856.3080216","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T23:37:15Z","timestamp":1750203435000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3079856.3080216"}},"subtitle":["A High-Level Performance Model for Hardware Accelerators"],"short-title":[],"issued":{"date-parts":[[2017,6,24]]},"references-count":54,"alternative-id":["10.1145\/3079856.3080216","10.1145\/3079856"],"URL":"https:\/\/doi.org\/10.1145\/3079856.3080216","relation":{"is-identical-to":[{"id-type":"doi","id":"10.1145\/3140659.3080216","asserted-by":"object"}]},"subject":[],"published":{"date-parts":[[2017,6,24]]},"assertion":[{"value":"2017-06-24","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}