{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,11]],"date-time":"2026-03-11T01:50:09Z","timestamp":1773193809678,"version":"3.50.1"},"publisher-location":"New York, NY, USA","reference-count":44,"publisher":"ACM","license":[{"start":{"date-parts":[[2017,6,24]],"date-time":"2017-06-24T00:00:00Z","timestamp":1498262400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","award":["IIS-1247701, CCF-1111943, CCF-1337375, and SHF-1408911"],"award-info":[{"award-number":["IIS-1247701, CCF-1111943, CCF-1337375, and SHF-1408911"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]},{"name":"Stanford PPL affiliates program, Pervasive Parallelism Lab: Oracle, AMD, Huawei, Intel, NVIDIA, SAP Labs"},{"name":"Army Contract AHPCRC","award":["W911NF-07-2-0027-1"],"award-info":[{"award-number":["W911NF-07-2-0027-1"]}]},{"name":"DARPA Contract-Air Force","award":["FA8750-12-2-0335"],"award-info":[{"award-number":["FA8750-12-2-0335"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2017,6,24]]},"DOI":"10.1145\/3079856.3080256","type":"proceedings-article","created":{"date-parts":[[2017,6,15]],"date-time":"2017-06-15T15:40:01Z","timestamp":1497541201000},"page":"389-402","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":207,"title":["Plasticine"],"prefix":"10.1145","author":[{"given":"Raghu","family":"Prabhakar","sequence":"first","affiliation":[{"name":"Stanford University"}]},{"given":"Yaqi","family":"Zhang","sequence":"additional","affiliation":[{"name":"Stanford University"}]},{"given":"David","family":"Koeplinger","sequence":"additional","affiliation":[{"name":"Stanford University"}]},{"given":"Matt","family":"Feldman","sequence":"additional","affiliation":[{"name":"Stanford University"}]},{"given":"Tian","family":"Zhao","sequence":"additional","affiliation":[{"name":"Stanford University"}]},{"given":"Stefan","family":"Hadjis","sequence":"additional","affiliation":[{"name":"Stanford University"}]},{"given":"Ardavan","family":"Pedram","sequence":"additional","affiliation":[{"name":"Stanford University"}]},{"given":"Christos","family":"Kozyrakis","sequence":"additional","affiliation":[{"name":"Stanford University"}]},{"given":"Kunle","family":"Olukotun","sequence":"additional","affiliation":[{"name":"Stanford University"}]}],"member":"320","published-online":{"date-parts":[[2017,6,24]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/1869459.1869469"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228584"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/2436696.2443836"},{"key":"e_1_3_2_1_4_1","unstructured":"Ivo Bolsens. 2006. Programming Modern FPGAs International Forum on Embedded Multiprocessor SoC Keynote . http:\/\/www.xilinx.com\/univ\/mpsoc2006keynote.pdf."},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2009.2037211"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/2.839323"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/2554688.2554787"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/1941553.1941562"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2014.58"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2016.7418007"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/2485922.2485945"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.5555\/786453.786708"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2009.5272293"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2016.7446059"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2014.6927454"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/300979.300982"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2012.51"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1815968"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2016.30"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2016.20"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.884574"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1561\/1000000005"},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2014.23"},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1145\/2485922.2485964"},{"key":"e_1_3_2_1_25_1","volume-title":"Hugo De Man, and Rudy Lauwereins","author":"Mei Bingfeng","year":"2003","unstructured":"Bingfeng Mei, Serge Vernalde, Diederik Verkest, Hugo De Man, and Rudy Lauwereins. 2003. ADRES: An Architecture with Tightly Coupled VLIW Processor and CoarseGrained Reconfigurable Matrix. Springer Berlin Heidelberg, Berlin, Heidelberg, 61--70."},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1145\/1168857.1168878"},{"key":"e_1_3_2_1_27_1","unstructured":"M. Odersky. 2011. Scala. http:\/\/www.scala-lang.org. (2011)."},{"key":"e_1_3_2_1_28_1","series-title":"Hot Chips 26","volume-title":"SDA: Software-Defined Accelerator for LargeScale DNN Systems","author":"Ouyang Jian","year":"2014","unstructured":"Jian Ouyang, Shiding Lin, Wei Qi, Yong Wang, Bo Yu, and Song Jiang. 2014. SDA: Software-Defined Accelerator for LargeScale DNN Systems (Hot Chips 26)."},{"key":"e_1_3_2_1_29_1","volume-title":"Chung","author":"Ovtcharov Kalin","year":"2015","unstructured":"Kalin Ovtcharov, Olatunji Ruwase, Joo-Young Kim, Jeremy Fowers, Karin Strauss, and Eric S. Chung. 2015. Accelerating Deep Convolutional Neural Networks Using Specialized Hardware. Technical Report. Microsoft Research. http:\/\/research-srv.microsoft.com\/pubs\/240715\/CNN%20Whitepaper.pdf"},{"key":"e_1_3_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1145\/2485922.2485935"},{"key":"e_1_3_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1109\/SBAC-PAD.2012.35"},{"key":"e_1_3_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1109\/MDAT.2016.2573586"},{"key":"e_1_3_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2012.132"},{"key":"e_1_3_2_1_34_1","volume-title":"Purely Functional Language. Available from http:\/\/www.haskell.org\/definition\/. (feb","author":"Simon Peyton","year":"1999","unstructured":"Simon Peyton Jones {editor}, John Hughes {editor}, Lennart Augustsson, Dave Barton, Brian Boutel, Warren Burton, Simon Fraser, Joseph Fasel, Kevin Hammond, Ralf Hinze, Paul Hudak, Thomas Johnsson, Mark Jones, John Launchbury, Erik Meijer, John Peterson, Alastair Reid, Colin Runciman, and Philip Wadler. 1999. Haskell 98 --- A Non-strict, Purely Functional Language. Available from http:\/\/www.haskell.org\/definition\/. (feb 1999)."},{"key":"e_1_3_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1145\/1059876.1059881"},{"key":"e_1_3_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1145\/2872362.2872415"},{"key":"e_1_3_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.5555\/2665671.2665678"},{"key":"e_1_3_2_1_38_1","doi-asserted-by":"publisher","DOI":"10.1145\/2491956.2462176"},{"key":"e_1_3_2_1_39_1","doi-asserted-by":"publisher","DOI":"10.1109\/L-CA.2011.4"},{"key":"e_1_3_2_1_40_1","doi-asserted-by":"publisher","DOI":"10.1145\/2584665"},{"key":"e_1_3_2_1_41_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-39038-8_3"},{"key":"e_1_3_2_1_42_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2002.997877"},{"key":"e_1_3_2_1_43_1","doi-asserted-by":"publisher","DOI":"10.5555\/2665671.2665703"},{"key":"e_1_3_2_1_44_1","doi-asserted-by":"publisher","DOI":"10.1145\/2541940.2541961"}],"event":{"name":"ISCA '17: The 44th Annual International Symposium on Computer Architecture","location":"Toronto ON Canada","acronym":"ISCA '17","sponsor":["IEEE IEEE Computer Society Technical Committee on Design Automation","SIGARCH ACM Special Interest Group on Computer Architecture"]},"container-title":["Proceedings of the 44th Annual International Symposium on Computer Architecture"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3079856.3080256","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3079856.3080256","content-type":"application\/pdf","content-version":"vor","intended-application":"syndication"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3079856.3080256","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T23:37:16Z","timestamp":1750203436000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3079856.3080256"}},"subtitle":["A Reconfigurable Architecture For Parallel Paterns"],"short-title":[],"issued":{"date-parts":[[2017,6,24]]},"references-count":44,"alternative-id":["10.1145\/3079856.3080256","10.1145\/3079856"],"URL":"https:\/\/doi.org\/10.1145\/3079856.3080256","relation":{"is-identical-to":[{"id-type":"doi","id":"10.1145\/3140659.3080256","asserted-by":"object"}]},"subject":[],"published":{"date-parts":[[2017,6,24]]},"assertion":[{"value":"2017-06-24","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}