{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:08:10Z","timestamp":1750306090581,"version":"3.41.0"},"reference-count":36,"publisher":"Association for Computing Machinery (ACM)","issue":"1","license":[{"start":{"date-parts":[[2017,8,31]],"date-time":"2017-08-31T00:00:00Z","timestamp":1504137600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Des. Autom. Electron. Syst."],"published-print":{"date-parts":[[2018,1,31]]},"abstract":"<jats:p>\n            Due to the increase in manufacturing\/environmental uncertainties in the nanometer regime, testing digital chips under different operating conditions becomes mandatory. Traditionally, stuck-at tests were applied at slow speed to detect structural defects and transition fault tests were applied at-speed to detect delay defects. Recently, it was shown that certain cell-internal defects can only be detected using\n            <jats:italic>at-speed stuck-at testing<\/jats:italic>\n            . Stuck-at test patterns are power hungry, thereby causing excessive voltage droop on the power grid, delaying the test response, and finally leading to false delay failures on the tester. This motivates the need for peak power minimization during at-speed stuck-at testing. In this article, we use input toggle minimization as a means to minimize a circuit\u2019s power dissipation during at-speed stuck-at testing under the Combinational State Preservation scan (CSP-scan) Design-For-Testability (DFT) scheme. For circuits whose test sets are dominated by don\u2019t cares, this article maps the problem of optimal X-filling for peak input toggle minimization to a variant of the interval coloring problem and proposes a Dynamic Programming (DP) algorithm (DP-fill) for the same along with a theoretical proof for its optimality. For circuits whose test sets are not dominated by don\u2019t cares, we propose a max scatter Hamiltonian path algorithm, which ensures that the ordering is done such that the don\u2019t cares are evenly distributed in the final ordering of test cubes, thereby leading to better input toggle savings than DP-fill. The proposed algorithms, when experimented on ITC99 benchmarks, produced peak power savings of up to 48% over the best-known algorithms in literature. We have also pruned the solutions thus obtained using Greedy and Simulated Annealing strategies with iterative 1-bit neighborhood to validate our idea of optimal input toggle minimization as an effective technique for minimizing peak power dissipation during at-speed stuck-at testing.\n          <\/jats:p>","DOI":"10.1145\/3084684","type":"journal-article","created":{"date-parts":[[2017,9,1]],"date-time":"2017-09-01T12:27:42Z","timestamp":1504268862000},"page":"1-26","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":4,"title":["Optimal Don\u2019t Care Filling for Minimizing Peak Toggles During At-Speed Stuck-At Testing"],"prefix":"10.1145","volume":"23","author":[{"given":"A. Satya","family":"Trinadh","sequence":"first","affiliation":[{"name":"Department of Computer Science and Engineering, IIT Hyderabad, Telangana, India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Seetal","family":"Potluri","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering, IIT Madras, Chennai, India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sobhan Babu","family":"Ch.","sequence":"additional","affiliation":[{"name":"Department of Computer Science and Engineering, IIT Hyderabad, Telangana, India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"V.","family":"Kamakoti","sequence":"additional","affiliation":[{"name":"Department of Computer Science and Engineering, IIT Madras, Chennai, India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Shiv Govind","family":"Singh","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering, IIT Hyderabad, Telangana, India"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2017,8,31]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/1146909.1146993"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2008.4700573"},{"key":"e_1_2_1_3_1","volume-title":"Arkin et al","author":"Esther","year":"1997","unstructured":"Esther M. Arkin et al . 1997 . On the maximum scatter TSP. In Symposium on Discrete Algorithms. ACM-SIAM , 211--220. Esther M. Arkin et al. 1997. On the maximum scatter TSP. In Symposium on Discrete Algorithms. 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Power-Aware Testing and Test of Low Power Design. Springer. 978-1-4419-0927-5  P. Girard N. Nicolici and X. Wen. 2009. Power-Aware Testing and Test of Low Power Design. Springer. 978-1-4419-0927-5"},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.1998.706917"},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.1999.810734"},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2010.59"},{"key":"e_1_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1007\/s10732-012-9194-6"},{"volume-title":"Asian Test Symposium. IEEE, 453--458","author":"Kuen-Jong","key":"e_1_2_1_19_1","unstructured":"Kuen-Jong Lee et al. 2000. Peak-power reduction for multiple-scan circuits during test application . In Asian Test Symposium. IEEE, 453--458 . Kuen-Jong Lee et al. 2000. Peak-power reduction for multiple-scan circuits during test application. In Asian Test Symposium. IEEE, 453--458."},{"key":"e_1_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2008.33"},{"key":"e_1_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2000.894222"},{"key":"e_1_2_1_23_1","volume-title":"International Test Conference. IEEE, 1--8.","author":"P. Pant","year":"2010","unstructured":"P. Pant et al. 2010 . Lessons from at-speed scan deployment on an Intel\u00aeItanium\u00ae microprocessor . In International Test Conference. IEEE, 1--8. P. Pant et al. 2010. Lessons from at-speed scan deployment on an Intel\u00aeItanium\u00ae microprocessor. In International Test Conference. IEEE, 1--8."},{"key":"e_1_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1109\/DFTVS.2004.1347857"},{"key":"e_1_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2014.2345762"},{"key":"e_1_2_1_26_1","unstructured":"S. Potluri. 2015. Power: Its Manifestations During Digital Systems Testing. Ph.D. Dissertation. Indian Institute of Technology Madras Chennai India.  S. Potluri. 2015. Power: Its Manifestations During Digital Systems Testing. Ph.D. Dissertation. Indian Institute of Technology Madras Chennai India."},{"key":"e_1_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2013.6657083"},{"key":"e_1_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1145\/2790297"},{"key":"e_1_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2002.1011127"},{"key":"e_1_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1166\/jolpe.2013.1255"},{"key":"e_1_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1166\/jolpe.2014.1302"},{"key":"e_1_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2003.1271098"},{"key":"e_1_2_1_33_1","unstructured":"Vlado Vorisek et al. 2004. At-speed testing of SOC ICs. In Design Automation and Test in Europe. IEEE 30120.  Vlado Vorisek et al. 2004. At-speed testing of SOC ICs. In Design Automation and Test in Europe. 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