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Code Optim."],"published-print":{"date-parts":[[2017,6,30]]},"abstract":"<jats:p>Historically, server designers have opted for simple memory systems by picking one of a few commoditized DDR memory products. We are already witnessing a major upheaval in the off-chip memory hierarchy, with the introduction of many new memory products\u2014buffer-on-board, LRDIMM, HMC, HBM, and NVMs, to name a few. Given the plethora of choices, it is expected that different vendors will adopt different strategies for their high-capacity memory systems, often deviating from DDR standards and\/or integrating new functionality within memory systems. These strategies will likely differ in their choice of interconnect and topology, with a significant fraction of memory energy being dissipated in I\/O and data movement. To make the case for memory interconnect specialization, this paper makes three contributions.<\/jats:p>\n          <jats:p>First, we design a tool that carefully models I\/O power in the memory system, explores the design space, and gives the user the ability to define new types of memory interconnects\/topologies. The tool is validated against SPICE models, and is integrated into version 7 of the popular CACTI package. Our analysis with the tool shows that several design parameters have a significant impact on I\/O power.<\/jats:p>\n          <jats:p>We then use the tool to help craft novel specialized memory system channels. We introduce a new relay-on-board chip that partitions a DDR channel into multiple cascaded channels. We show that this simple change to the channel topology can improve performance by 22% for DDR DRAM and lower cost by up to 65% for DDR DRAM. This new architecture does not require any changes to DIMMs, and it efficiently supports hybrid DRAM\/NVM systems.<\/jats:p>\n          <jats:p>Finally, as an example of a more disruptive architecture, we design a custom DIMM and parallel bus that moves away from the DDR3\/DDR4 standards. To reduce energy and improve performance, the baseline data channel is split into three narrow parallel channels and the on-DIMM interconnects are operated at a lower frequency. In addition, this allows us to design a two-tier error protection strategy that reduces data transfers on the interconnect. This architecture yields a performance improvement of 18% and a memory power reduction of 23%.<\/jats:p>\n          <jats:p>The cascaded channel and narrow channel architectures serve as case studies for the new tool and show the potential for benefit from re-organizing basic memory interconnects.<\/jats:p>","DOI":"10.1145\/3085572","type":"journal-article","created":{"date-parts":[[2017,6,30]],"date-time":"2017-06-30T12:36:19Z","timestamp":1498826179000},"page":"1-25","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":474,"title":["CACTI 7"],"prefix":"10.1145","volume":"14","author":[{"given":"Rajeev","family":"Balasubramonian","sequence":"first","affiliation":[{"name":"University of Utah"}]},{"given":"Andrew B.","family":"Kahng","sequence":"additional","affiliation":[{"name":"University of California, San Diego"}]},{"given":"Naveen","family":"Muralimanohar","sequence":"additional","affiliation":[{"name":"Hewlett Packard Labs"}]},{"given":"Ali","family":"Shafiee","sequence":"additional","affiliation":[{"name":"University of Utah"}]},{"given":"Vaishnav","family":"Srinivas","sequence":"additional","affiliation":[{"name":"University of California, San Diego"}]}],"member":"320","published-online":{"date-parts":[[2017,6,28]]},"reference":[{"key":"e_1_2_2_1_1","volume-title":"TE DDR2 Connector Model. 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