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Model. Perform. Eval. Comput. Syst."],"published-print":{"date-parts":[[2017,9,30]]},"abstract":"<jats:p>Future servers will incorporate many active low-power modes for each core and for the main memory subsystem. Though these modes provide flexibility for power and\/or energy management via Dynamic Voltage and Frequency Scaling (DVFS), prior work has shown that they must be managed in a coordinated manner. This requirement creates a combinatorial space of possible power mode configurations. As a result, it becomes increasingly challenging to quickly select the configuration that optimizes for both performance and power\/energy efficiency.<\/jats:p>\n          <jats:p>In this article, we propose a novel queuing model for working with the abundant active low-power modes in many-core systems. Based on the queuing model, we derive two fast algorithms that optimize for performance and efficiency using both CPU and memory DVFS. Our first algorithm, called FastCap, maximizes the performance of applications under a full-system power cap, while promoting fairness across applications. Our second algorithm, called FastEnergy, maximizes the full-system energy savings under predefined application performance loss bounds. Both FastCap and FastEnergy operate online and efficiently, using a small set of performance counters as input. To evaluate them, we simulate both algorithms for a many-core server running different types of workloads. Our results show that FastCap achieves better application performance and fairness than prior power capping techniques for the same power budget, whereas FastEnergy conserves more energy than prior energy management techniques for the same performance constraint. FastCap and FastEnergy together demonstrate the applicability of the queuing model for managing the abundant active low-power modes in many-core systems.<\/jats:p>","DOI":"10.1145\/3086504","type":"journal-article","created":{"date-parts":[[2017,9,5]],"date-time":"2017-09-05T12:23:34Z","timestamp":1504614214000},"page":"1-31","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":4,"title":["Fast Power and Energy Management for Future Many-Core Systems"],"prefix":"10.1145","volume":"2","author":[{"given":"Yanpei","family":"Liu","sequence":"first","affiliation":[{"name":"University of Wisconsin Madison, Madison, WI"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Guilherme","family":"Cox","sequence":"additional","affiliation":[{"name":"Rutgers University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Qingyuan","family":"Deng","sequence":"additional","affiliation":[{"name":"Facebook Inc., Menlo Park, CA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Stark C.","family":"Draper","sequence":"additional","affiliation":[{"name":"University of Toronto, Toronto, Ontario"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ricardo","family":"Bianchini","sequence":"additional","affiliation":[{"name":"Microsoft Research, Redmond, WA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2017,9,5]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1816004"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/32.4623"},{"key":"e_1_2_1_3_1","doi-asserted-by":"crossref","unstructured":"S. Balsamo V. D. N. Persone and R. Onvural. 2001. Analysis of Queuing Networks with Blocking. Springer.   S. Balsamo V. D. N. Persone and R. Onvural. 2001. Analysis of Queuing Networks with Blocking. Springer.","DOI":"10.1007\/978-1-4757-3345-7"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/1206035.1206038"},{"volume-title":"Proceedings of the IEEE International Conference on Computer Design.","author":"Begum R.","key":"e_1_2_1_5_1","unstructured":"R. Begum , M. Hempstead , G. P. Srinivasa , and G. Challen . 2016. Algorithms for CPU and DRAM DVFS under inefficiency constraints . In Proceedings of the IEEE International Conference on Computer Design. R. Begum, M. Hempstead, G. P. Srinivasa, and G. Challen. 2016. Algorithms for CPU and DRAM DVFS under inefficiency constraints. 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