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Code Optim."],"published-print":{"date-parts":[[2017,6,30]]},"abstract":"<jats:p>Increasing instruction-level parallelism is regaining attractiveness within the microprocessor industry.<\/jats:p>\n          <jats:p>The {Early | Out-of-order | Late} Execution (EOLE) microarchitecture and Differential Value TAgged GEometric (D-VTAGE) value predictor were recently introduced to solve practical issues of Value Prediction (VP). In particular, they remove the most significant difficulties that forbade an effective VP hardware.<\/jats:p>\n          <jats:p>In this study, we present a detailed evaluation of the potential of VP in the context of EOLE\/D-VTAGE and different compiler options. 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Chrysos and Joel S. Emer. 1998. Memory dependence prediction using store sets. In Proceedings of the 25th Annual International Symposium on Computer Architecture (ISCA\u201998). IEEE Computer Society, Washington, DC, 142--153. DOI:http:\/\/dx.doi.org\/10.1145\/279358.279378"},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/2000064.2000108"},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/290409.290411"},{"key":"e_1_2_1_10_1","unstructured":"Intel. 2015. Intel 64 and IA-32 Architectures Optimization Reference Manual.  Intel. 2015. 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