{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,28]],"date-time":"2025-10-28T15:00:47Z","timestamp":1761663647657,"version":"3.41.0"},"reference-count":45,"publisher":"Association for Computing Machinery (ACM)","issue":"1","license":[{"start":{"date-parts":[[2017,9,21]],"date-time":"2017-09-21T00:00:00Z","timestamp":1505952000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["J. Emerg. Technol. Comput. Syst."],"published-print":{"date-parts":[[2018,1,31]]},"abstract":"<jats:p>Three-dimensional DRAMs (3D-DRAMs) are emerging as a promising solution to address the memory wall problem in computer systems. However, high fabrication cost per bit and thermal issues are the main reasons that prevent architects from using 3D-DRAM alone as the main memory building block. In this article, we address this issue by proposing a heterogeneous memory system that combines a double data rate (DDRx) DRAM with an emerging 3D hybrid memory cube (HMC) technology. Bandwidth and temperature management are the challenging issues for this heterogeneous memory architecture. To address these challenges, first we introduce a memory page allocation policy for the heterogeneous memory system to maximize performance. Then, using the proposed policy, we introduce a temperature-aware algorithm that dynamically distributes the requested bandwidth between HMC and DDRx DRAM to reduce the thermal hotspot while maintaining high performance. We take into account the impact of both core count and HMC channel count on performance while using the proposed policies. The results show that the proposed memory page allocation policy can utilize the memory bandwidth close to 99% of the ideal bandwidth utilization. Moreover, our temperate-aware bandwidth adaptation reduces the average steady-state temperature of the HMC hotspot across various workloads by 4.5 K while incurring 2.5% performance overhead.<\/jats:p>","DOI":"10.1145\/3106233","type":"journal-article","created":{"date-parts":[[2017,9,25]],"date-time":"2017-09-25T13:03:12Z","timestamp":1506344592000},"page":"1-21","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":5,"title":["Heterogeneous HMC+DDRx Memory Management for Performance-Temperature Tradeoffs"],"prefix":"10.1145","volume":"14","author":[{"given":"Mohammad Hossein","family":"Hajkazemi","sequence":"first","affiliation":[{"name":"George Mason University"}]},{"given":"Mohammad Khavari","family":"Tavana","sequence":"additional","affiliation":[{"name":"George Mason University"}]},{"given":"Tinoosh","family":"Mohsenin","sequence":"additional","affiliation":[{"name":"University of Maryland Baltimore County, Baltimore, MD"}]},{"given":"Houman","family":"Homayoun","sequence":"additional","affiliation":[{"name":"George Mason University"}]}],"member":"320","published-online":{"date-parts":[[2017,9,21]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/2593069.2593128"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2015.2420315"},{"key":"e_1_2_1_3_1","unstructured":"Greg Atwood. 2011. Current and Emerging Memory Technology Landscape. Retrieved from http:\/\/www.flashmemorysummit.com\/English\/Collaterals\/Proceedings\/2011\/20110811_S303_Atwood.pdf.  Greg Atwood. 2011. Current and Emerging Memory Technology Landscape. Retrieved from http:\/\/www.flashmemorysummit.com\/English\/Collaterals\/Proceedings\/2011\/20110811_S303_Atwood.pdf."},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1177\/109434209100500306"},{"key":"e_1_2_1_5_1","unstructured":"Samta Bansal. 2011. 3D-IC Is Now Real: Wide-IO Is Driving 3D-IC TSV. Retrieved from http:\/\/www.flashmemorysummit.com\/English\/Collaterals\/Proceedings\/2012\/20120821_S101A_Bansal.pdf.  Samta Bansal. 2011. 3D-IC Is Now Real: Wide-IO Is Driving 3D-IC TSV. Retrieved from http:\/\/www.flashmemorysummit.com\/English\/Collaterals\/Proceedings\/2012\/20120821_S101A_Bansal.pdf."},{"key":"e_1_2_1_6_1","unstructured":"Bob Brennan. 2013. New Directions in Memory Architecture. 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Retrieved from http:\/\/www.memcon.com\/pdfs\/keynote_scottgraham.pdf."},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/CODES-ISSS.2013.6658989"},{"key":"e_1_2_1_13_1","unstructured":"Marc Greenberg. 2012. How do I decide? Is LPDDR3 or Wide I\/O the right memory technology for my next smartphone and tablet? Retrieved from http:\/\/www.jedec.org\/sites\/default\/files\/Mgreenberg20-20Cadence20-Taiwan_and_Korea_8_17_2012.pdf.  Marc Greenberg. 2012. How do I decide? Is LPDDR3 or Wide I\/O the right memory technology for my next smartphone and tablet? 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