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In this article, we propose an advanced SBUS protocol (ASBUS), to improve the data feeding efficiency of the Advanced Encryption Standard (AES) encrypted circuits. As a case study, the direct memory access (DMA) combined with AES engine and memory controller are implemented as our design-under-test (DUT) using field-programmable gate arrays (FPGA). The results show that our presented ASBUS structure outperforms the AXI-based design for cipher tests. As an example, the 32-bit ASBUS design costs less in terms of hardware resources and achieves higher throughput (1.30 \u00d7) than the 32-bit AXI implementation, and the dynamic energy consumed by the ASBUS cipher test is reduced to 71.27% compared with the AXI test.<\/jats:p>","DOI":"10.1145\/3110713","type":"journal-article","created":{"date-parts":[[2017,12,13]],"date-time":"2017-12-13T14:50:37Z","timestamp":1513176637000},"page":"1-23","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":9,"title":["Improving AES Core Performance via an Advanced ASBUS Protocol"],"prefix":"10.1145","volume":"14","author":[{"given":"Xiaokun","family":"Yang","sequence":"first","affiliation":[{"name":"University of Houston Clear Lake"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Wujie","family":"Wen","sequence":"additional","affiliation":[{"name":"Florida International University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ming","family":"Fan","sequence":"additional","affiliation":[{"name":"Broadcom Corporation"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2017,12,11]]},"reference":[{"key":"e_1_2_1_1_1","unstructured":"1999. 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