{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,19]],"date-time":"2026-03-19T11:13:13Z","timestamp":1773918793965,"version":"3.50.1"},"publisher-location":"New York, NY, USA","reference-count":69,"publisher":"ACM","license":[{"start":{"date-parts":[[2017,10,14]],"date-time":"2017-10-14T00:00:00Z","timestamp":1507939200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","award":["XPS-1438996,SHF-1527301"],"award-info":[{"award-number":["XPS-1438996,SHF-1527301"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2017,10,14]]},"DOI":"10.1145\/3123939.3123974","type":"proceedings-article","created":{"date-parts":[[2017,10,4]],"date-time":"2017-10-04T18:06:06Z","timestamp":1507140366000},"page":"151-164","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":27,"title":["Regless"],"prefix":"10.1145","author":[{"given":"John","family":"Kloosterman","sequence":"first","affiliation":[{"name":"University of Michigan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jonathan","family":"Beaumont","sequence":"additional","affiliation":[{"name":"University of Michigan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"D. Anoushe","family":"Jamshidi","sequence":"additional","affiliation":[{"name":"University of Michigan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jonathan","family":"Bailey","sequence":"additional","affiliation":[{"name":"University of Michigan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Trevor","family":"Mudge","sequence":"additional","affiliation":[{"name":"University of Michigan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Scott","family":"Mahlke","sequence":"additional","affiliation":[{"name":"University of Michigan"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2017,10,14]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2013.6522337"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2015.55"},{"key":"e_1_3_2_1_3_1","first-page":"133","volume-title":"Taming control divergence in gpus through control flow linearization,\" in International Conference on Compiler Construction","author":"Anantpur J.","year":"2014","unstructured":"J. Anantpur and R. Govindarajan , \" Taming control divergence in gpus through control flow linearization,\" in International Conference on Compiler Construction . Springer , 2014 , pp. 133 -- 153 . J. Anantpur and R. Govindarajan, \"Taming control divergence in gpus through control flow linearization,\" in International Conference on Compiler Construction. Springer, 2014, pp. 133--153."},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2015.38"},{"key":"e_1_3_2_1_5_1","first-page":"163","volume-title":"ISPASS 2009. IEEE International Symposium on. IEEE","author":"Bakhoda A.","year":"2009","unstructured":"A. Bakhoda , G. L. Yuan , W. W. Fung , H. Wong , and T. M. Aamodt , \" Analyzing cuda workloads using a detailed gpu simulator,\" in Performance Analysis of Systems and Software, 2009 . ISPASS 2009. IEEE International Symposium on. IEEE , 2009 , pp. 163 -- 174 . A. Bakhoda, G. L. Yuan, W. W. Fung, H. Wong, and T. M. Aamodt, \"Analyzing cuda workloads using a detailed gpu simulator,\" in Performance Analysis of Systems and Software, 2009. ISPASS 2009. IEEE International Symposium on. IEEE, 2009, pp. 163--174."},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2009.5306797"},{"key":"e_1_3_2_1_7_1","volume-title":"Mimd synchronization on simt architectures,\" in Proceedings of the 49th annual IEEE\/ACM International Symposium on Microarchitecture","author":"ElTantawy A.","year":"2016","unstructured":"A. ElTantawy and T. M. Aamodt , \" Mimd synchronization on simt architectures,\" in Proceedings of the 49th annual IEEE\/ACM International Symposium on Microarchitecture , 2016 . A. ElTantawy and T. M. Aamodt, \"Mimd synchronization on simt architectures,\" in Proceedings of the 49th annual IEEE\/ACM International Symposium on Microarchitecture, 2016."},{"key":"e_1_3_2_1_8_1","first-page":"248","volume-title":"IEEE","author":"ElTantawy A.","year":"2014","unstructured":"A. ElTantawy , J. W. Ma , M. O'Connor , and T. M. Aamodt , \" A scalable multi-path microarchitecture for efficient gpu control flow,\" in 2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA) . IEEE , 2014 , pp. 248 -- 259 . A. ElTantawy, J. W. Ma, M. O'Connor, and T. M. Aamodt, \"A scalable multi-path microarchitecture for efficient gpu control flow,\" in 2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA). IEEE, 2014, pp. 248--259."},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/2024723.2000093"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/2166879.2166882"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/2155620.2155675"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2012.18"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/1508244.1508246"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2013.6522330"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2013.6522331"},{"key":"e_1_3_2_1_16_1","volume-title":"Fine-grained resource sharing for concurrent gpgpu kernels,\" in Presented as part of the 4th USENIX Workshop on Hot Topics in Parallelism","author":"Gregg C.","year":"2012","unstructured":"C. Gregg , J. Dorn , K. Hazelwood , and K. Skadron , \" Fine-grained resource sharing for concurrent gpgpu kernels,\" in Presented as part of the 4th USENIX Workshop on Hot Topics in Parallelism , 2012 . C. Gregg, J. Dorn, K. Hazelwood, and K. Skadron, \"Fine-grained resource sharing for concurrent gpgpu kernels,\" in Presented as part of the 4th USENIX Workshop on Hot Topics in Parallelism, 2012."},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2016.27"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/2628071.2628101"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/2830772.2830784"},{"key":"e_1_3_2_1_20_1","first-page":"55","volume-title":"2015 IEEE\/ACM International Symposium on. IEEE","author":"Jing N.","year":"2015","unstructured":"N. Jing , S. Chen , S. Jiang , L. Jiang , C. Li , and X. Liang , \" Bank stealing for conflict mitigation in gpgpu register file,\" in Low Power Electronics and Design (ISLPED) , 2015 IEEE\/ACM International Symposium on. IEEE , 2015 , pp. 55 -- 60 . N. Jing, S. Chen, S. Jiang, L. Jiang, C. Li, and X. Liang, \"Bank stealing for conflict mitigation in gpgpu register file,\" in Low Power Electronics and Design (ISLPED), 2015 IEEE\/ACM International Symposium on. IEEE, 2015, pp. 55--60."},{"key":"e_1_3_2_1_21_1","first-page":"3","volume-title":"Compiler assisted dynamic register file in gpgpu,\" in Proceedings of the 2013 International Symposium on Low Power Electronics and Design","author":"Jing N.","year":"2013","unstructured":"N. Jing , H. Liu , Y. Lu , and X. Liang , \" Compiler assisted dynamic register file in gpgpu,\" in Proceedings of the 2013 International Symposium on Low Power Electronics and Design . IEEE Press , 2013 , pp. 3 -- 8 . N. Jing, H. Liu, Y. Lu, and X. Liang, \"Compiler assisted dynamic register file in gpgpu,\" in Proceedings of the 2013 International Symposium on Low Power Electronics and Design. IEEE Press, 2013, pp. 3--8."},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/2508148.2485952"},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2016.7783717"},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1145\/2499368.2451158"},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1145\/2508148.2485951"},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1145\/2896377.2901468"},{"key":"e_1_3_2_1_27_1","first-page":"157","volume-title":"Neither more nor less: optimizing thread-level parallelism for gpgpus,\" in Proceedings of the 22nd international conference on Parallel architectures and compilation techniques","author":"Kay\u0131ran O.","year":"2013","unstructured":"O. Kay\u0131ran , A. Jog , M. T. Kandemir , and C. R. Das , \" Neither more nor less: optimizing thread-level parallelism for gpgpus,\" in Proceedings of the 22nd international conference on Parallel architectures and compilation techniques . IEEE Press , 2013 , pp. 157 -- 166 . O. Kay\u0131ran, A. Jog, M. T. Kandemir, and C. R. Das, \"Neither more nor less: optimizing thread-level parallelism for gpgpus,\" in Proceedings of the 22nd international conference on Parallel architectures and compilation techniques. IEEE Press, 2013, pp. 157--166."},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1145\/2967938.2967941"},{"key":"e_1_3_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2011.89"},{"key":"e_1_3_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1145\/2508148.2485934"},{"key":"e_1_3_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1145\/2749469.2750417"},{"key":"e_1_3_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1145\/2749469.2750418"},{"key":"e_1_3_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1145\/2508148.2485964"},{"key":"e_1_3_2_1_34_1","first-page":"161","article-title":"Gpu voltage noise: Characterization and hierarchical smoothing of spatial and temporal voltage noise interference in gpu architectures,\" in 2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA)","author":"Leng J.","year":"2015","unstructured":"J. Leng , Y. Zu , and V. J. Reddi , \" Gpu voltage noise: Characterization and hierarchical smoothing of spatial and temporal voltage noise interference in gpu architectures,\" in 2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA) . IEEE , 2015 , pp. 161 -- 173 . J. Leng, Y. Zu, and V. J. Reddi, \"Gpu voltage noise: Characterization and hierarchical smoothing of spatial and temporal voltage noise interference in gpu architectures,\" in 2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA). IEEE, 2015, pp. 161--173.","journal-title":"IEEE"},{"key":"e_1_3_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1145\/2627369.2627605"},{"key":"e_1_3_2_1_36_1","first-page":"23","volume-title":"2015 IEEE\/ACM International Symposium on. IEEE","author":"Li C.","year":"2015","unstructured":"C. Li , Y. Yang , Z. Lin , and H. Zhou , \" Automatic data placement into gpu on-chip memory resources,\" in Code Generation and Optimization (CGO) , 2015 IEEE\/ACM International Symposium on. IEEE , 2015 , pp. 23 -- 33 . C. Li, Y. Yang, Z. Lin, and H. Zhou, \"Automatic data placement into gpu on-chip memory resources,\" in Code Generation and Optimization (CGO), 2015 IEEE\/ACM International Symposium on. IEEE, 2015, pp. 23--33."},{"key":"e_1_3_2_1_37_1","first-page":"89","volume-title":"IEEE","author":"Li D.","year":"2015","unstructured":"D. Li , M. Rhu , D. R. Johnson , M. O'Connor , M. Erez , D. Burger , D. S. Fussell , and S. W. Redder , \" Priority-based cache allocation in throughput processors,\" in 2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA) . IEEE , 2015 , pp. 89 -- 100 . D. Li, M. Rhu, D. R. Johnson, M. O'Connor, M. Erez, D. Burger, D. S. Fussell, and S. W. Redder, \"Priority-based cache allocation in throughput processors,\" in 2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA). IEEE, 2015, pp. 89--100."},{"key":"e_1_3_2_1_38_1","first-page":"112","volume-title":"2013 14th International Symposium on. IEEE","author":"Li Z.","year":"2013","unstructured":"Z. Li , J. Tan , and X. Fu , \" Hybrid cmos-tfet based register files for energy-efficient gpgpus,\" in Quality Electronic Design (ISQED) , 2013 14th International Symposium on. IEEE , 2013 , pp. 112 -- 119 . Z. Li, J. Tan, and X. Fu, \"Hybrid cmos-tfet based register files for energy-efficient gpgpus,\" in Quality Electronic Design (ISQED), 2013 14th International Symposium on. IEEE, 2013, pp. 112--119."},{"key":"e_1_3_2_1_39_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.37"},{"key":"e_1_3_2_1_40_1","doi-asserted-by":"publisher","DOI":"10.1145\/2925426.2926267"},{"key":"e_1_3_2_1_41_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2017.51"},{"key":"e_1_3_2_1_42_1","doi-asserted-by":"publisher","DOI":"10.1145\/2593069.2593137"},{"key":"e_1_3_2_1_43_1","doi-asserted-by":"publisher","DOI":"10.1007\/BF02577867"},{"key":"e_1_3_2_1_44_1","volume-title":"Argo: aging-aware gpgpu register file allocation,\" in Proceedings of the Ninth IEEE\/ACM\/IFIP International Conference on Hardware\/Software Codesign and System Synthesis","author":"Namaki-Shoushtari M.","year":"2013","unstructured":"M. Namaki-Shoushtari , A. Rahimi , N. Dutt , P. Gupta , and R. K. Gupta , \" Argo: aging-aware gpgpu register file allocation,\" in Proceedings of the Ninth IEEE\/ACM\/IFIP International Conference on Hardware\/Software Codesign and System Synthesis . IEEE Press , 2013 , p. 30. M. Namaki-Shoushtari, A. Rahimi, N. Dutt, P. Gupta, and R. K. Gupta, \"Argo: aging-aware gpgpu register file allocation,\" in Proceedings of the Ninth IEEE\/ACM\/IFIP International Conference on Hardware\/Software Codesign and System Synthesis. IEEE Press, 2013, p. 30."},{"key":"e_1_3_2_1_45_1","doi-asserted-by":"publisher","DOI":"10.1145\/2155620.2155656"},{"key":"e_1_3_2_1_46_1","volume-title":"accessed","year":"2017","unstructured":"Nvidia, \"Nvidia cuda programming guide,\" http:\/\/docs.nvidia.com\/cuda\/cuda-c-programming-guide , accessed : August 2017 . Nvidia, \"Nvidia cuda programming guide,\" http:\/\/docs.nvidia.com\/cuda\/cuda-c-programming-guide, accessed: August 2017."},{"key":"e_1_3_2_1_47_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2005.21"},{"key":"e_1_3_2_1_48_1","doi-asserted-by":"publisher","DOI":"10.1145\/2451116.2451160"},{"key":"e_1_3_2_1_49_1","doi-asserted-by":"publisher","DOI":"10.1145\/2807591.2807598"},{"key":"e_1_3_2_1_50_1","first-page":"188","volume-title":"IEEE","author":"Pekhimenko G.","year":"2016","unstructured":"G. Pekhimenko , E. Bolotin , N. Vijaykumar , O. Mutlu , T. C. Mowry , and S. W. Keckler , \" A case for toggle-aware compression for gpu systems,\" in 2016 IEEE International Symposium on High Performance Computer Architecture (HPCA) . IEEE , 2016 , pp. 188 -- 200 . G. Pekhimenko, E. Bolotin, N. Vijaykumar, O. Mutlu, T. C. Mowry, and S. W. Keckler, \"A case for toggle-aware compression for gpu systems,\" in 2016 IEEE International Symposium on High Performance Computer Architecture (HPCA). IEEE, 2016, pp. 188--200."},{"key":"e_1_3_2_1_51_1","doi-asserted-by":"publisher","DOI":"10.1145\/2370816.2370870"},{"key":"e_1_3_2_1_52_1","doi-asserted-by":"publisher","DOI":"10.1145\/2654822.2541942"},{"key":"e_1_3_2_1_53_1","first-page":"258","volume-title":"PACT 2003. Proceedings. 12th International Conference on. IEEE","author":"Ponomarev D.","year":"2003","unstructured":"D. Ponomarev , G. Kucuk , O. Ergin , and K. Ghose , \" Reducing datapath energy through the isolation of short-lived operands,\" in Parallel Architectures and Compilation Techniques, 2003 . PACT 2003. Proceedings. 12th International Conference on. IEEE , 2003 , pp. 258 -- 268 . D. Ponomarev, G. Kucuk, O. Ergin, and K. Ghose, \"Reducing datapath energy through the isolation of short-lived operands,\" in Parallel Architectures and Compilation Techniques, 2003. PACT 2003. Proceedings. 12th International Conference on. IEEE, 2003, pp. 258--268."},{"key":"e_1_3_2_1_54_1","doi-asserted-by":"publisher","DOI":"10.1145\/2508148.2485953"},{"key":"e_1_3_2_1_55_1","doi-asserted-by":"publisher","DOI":"10.1145\/2749469.2750410"},{"key":"e_1_3_2_1_56_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2012.16"},{"key":"e_1_3_2_1_57_1","doi-asserted-by":"publisher","DOI":"10.1109\/L-CA.2007.15"},{"key":"e_1_3_2_1_58_1","doi-asserted-by":"publisher","DOI":"10.1145\/859618.859667"},{"key":"e_1_3_2_1_59_1","doi-asserted-by":"publisher","DOI":"10.1145\/2749469.2750375"},{"key":"e_1_3_2_1_60_1","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2015.57"},{"key":"e_1_3_2_1_61_1","first-page":"369","volume-title":"Automation & Test in Europe Conference & Exhibition (DATE). IEEE","author":"Tan J.","year":"2015","unstructured":"J. Tan , Z. Li , and X. Fu , \" Soft-error reliability and power co-optimization for gpgpus register file using resistive memory,\" in 2015 Design , Automation & Test in Europe Conference & Exhibition (DATE). IEEE , 2015 , pp. 369 -- 374 . J. Tan, Z. Li, and X. Fu, \"Soft-error reliability and power co-optimization for gpgpus register file using resistive memory,\" in 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 2015, pp. 369--374."},{"key":"e_1_3_2_1_62_1","doi-asserted-by":"publisher","DOI":"10.1145\/2967938.2967951"},{"key":"e_1_3_2_1_63_1","volume-title":"Zorua: A holistic approach to resource virtualization in gpus,\" in Proceedings of the 49th annual IEEE\/ACM International Symposium on Microarchitecture","author":"Vijaykumar N.","year":"2016","unstructured":"N. Vijaykumar , K. Hsieh , G. Pekhimenko , S. Khan , A. Shrestha , S. Ghose , A. Jog , P. B. Gibbons , and O. Mutlu , \" Zorua: A holistic approach to resource virtualization in gpus,\" in Proceedings of the 49th annual IEEE\/ACM International Symposium on Microarchitecture , 2016 . N. Vijaykumar, K. Hsieh, G. Pekhimenko, S. Khan, A. Shrestha, S. Ghose, A. Jog, P. B. Gibbons, and O. Mutlu, \"Zorua: A holistic approach to resource virtualization in gpus,\" in Proceedings of the 49th annual IEEE\/ACM International Symposium on Microarchitecture, 2016."},{"key":"e_1_3_2_1_64_1","doi-asserted-by":"publisher","DOI":"10.1145\/2749469.2750399"},{"key":"e_1_3_2_1_65_1","first-page":"25","volume-title":"IEEE","author":"Wang S.","year":"2016","unstructured":"S. Wang , Y. Liang , C. Zhang , X. Xie , G. Sun , Y. Liu , Y. Wang , and X. Li , \" Performance-centric register file design for gpus using racetrack memory,\" in 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC) . IEEE , 2016 , pp. 25 -- 30 . S. Wang, Y. Liang, C. Zhang, X. Xie, G. Sun, Y. Liu, Y. Wang, and X. Li, \"Performance-centric register file design for gpus using racetrack memory,\" in 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC). IEEE, 2016, pp. 25--30."},{"key":"e_1_3_2_1_66_1","doi-asserted-by":"publisher","DOI":"10.1145\/2751205.2751213"},{"key":"e_1_3_2_1_67_1","doi-asserted-by":"publisher","DOI":"10.1145\/2830772.2830813"},{"key":"e_1_3_2_1_68_1","doi-asserted-by":"publisher","DOI":"10.1145\/1328195.1328198"},{"key":"e_1_3_2_1_69_1","doi-asserted-by":"publisher","DOI":"10.1145\/2024723.2000094"}],"event":{"name":"MICRO-50: The 50th Annual IEEE\/ACM International Symposium on Microarchitecture","location":"Cambridge Massachusetts","acronym":"MICRO-50","sponsor":["SIGMICRO ACM Special Interest Group on Microarchitectural Research and Processing","IEEE-CS\\DATC IEEE Computer Society"]},"container-title":["Proceedings of the 50th Annual IEEE\/ACM International Symposium on Microarchitecture"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3123939.3123974","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3123939.3123974","content-type":"application\/pdf","content-version":"vor","intended-application":"syndication"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3123939.3123974","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T03:30:31Z","timestamp":1750217431000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3123939.3123974"}},"subtitle":["just-in-time operand staging for GPUs"],"short-title":[],"issued":{"date-parts":[[2017,10,14]]},"references-count":69,"alternative-id":["10.1145\/3123939.3123974","10.1145\/3123939"],"URL":"https:\/\/doi.org\/10.1145\/3123939.3123974","relation":{},"subject":[],"published":{"date-parts":[[2017,10,14]]},"assertion":[{"value":"2017-10-14","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}