{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,3]],"date-time":"2026-07-03T11:02:09Z","timestamp":1783076529928,"version":"3.54.6"},"publisher-location":"New York, NY, USA","reference-count":116,"publisher":"ACM","license":[{"start":{"date-parts":[[2017,10,14]],"date-time":"2017-10-14T00:00:00Z","timestamp":1507939200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","award":["1409723,1618563"],"award-info":[{"award-number":["1409723,1618563"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2017,10,14]]},"DOI":"10.1145\/3123939.3123975","type":"proceedings-article","created":{"date-parts":[[2017,10,4]],"date-time":"2017-10-04T18:06:06Z","timestamp":1507140366000},"page":"136-150","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":85,"title":["Mosaic"],"prefix":"10.1145","author":[{"given":"Rachata","family":"Ausavarungnirun","sequence":"first","affiliation":[{"name":"Carnegie Mellon University"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Joshua","family":"Landgraf","sequence":"additional","affiliation":[{"name":"University of Texas at Austin"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Vance","family":"Miller","sequence":"additional","affiliation":[{"name":"University of Texas at Austin"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Saugata","family":"Ghose","sequence":"additional","affiliation":[{"name":"Carnegie Mellon University"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Jayneel","family":"Gandhi","sequence":"additional","affiliation":[{"name":"VMware Research"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Christopher J.","family":"Rossbach","sequence":"additional","affiliation":[{"name":"University of Texas at Austin and VMware Research"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Onur","family":"Mutlu","sequence":"additional","affiliation":[{"name":"ETH Z\u00fcrich and Carnegie Mellon University"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2017,10,14]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"A. Abrevaya \"Linux Transparent Huge Pages JEMalloc and NuoDB \" 2014.  A. Abrevaya \"Linux Transparent Huge Pages JEMalloc and NuoDB \" 2014."},{"key":"e_1_3_2_1_2_1","unstructured":"Advanced Micro Devices Inc. \"OpenCL: The Future of Accelerated Application Performance Is Now \" https:\/\/www.amd.com\/Documents\/FirePro_OpenCL_Whitepaper.pdf.  Advanced Micro Devices Inc. \"OpenCL: The Future of Accelerated Application Performance Is Now \" https:\/\/www.amd.com\/Documents\/FirePro_OpenCL_Whitepaper.pdf."},{"key":"e_1_3_2_1_3_1","volume-title":"Unlocking Bandwidth for GPUs in CC-NUMA Systems,\" in HPCA","author":"Agarwal N.","year":"2015","unstructured":"N. Agarwal , D. Nellans , M. O'Connor , S. W. Keckler , and T. F. Wenisch , \" Unlocking Bandwidth for GPUs in CC-NUMA Systems,\" in HPCA , 2015 . N. Agarwal, D. Nellans, M. O'Connor, S. W. Keckler, and T. F. Wenisch, \"Unlocking Bandwidth for GPUs in CC-NUMA Systems,\" in HPCA, 2015."},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/2366231.2337214"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2015.2401022"},{"key":"e_1_3_2_1_6_1","unstructured":"Apple Inc. \"Huge Page Support in Mac OS X \" http:\/\/blog.couchbase.com\/often-overlooked-linux-os-tweaks 2014.  Apple Inc. \"Huge Page Support in Mac OS X \" http:\/\/blog.couchbase.com\/often-overlooked-linux-os-tweaks 2014."},{"key":"e_1_3_2_1_7_1","unstructured":"ARM Holdings \"ARM Cortex-A Series \" http:\/\/infocenter.arm.com\/help\/topic\/com.arm.doc.den0024a\/DEN0024A_v8_architecture_PG.pdf 2015.  ARM Holdings \"ARM Cortex-A Series \" http:\/\/infocenter.arm.com\/help\/topic\/com.arm.doc.den0024a\/DEN0024A_v8_architecture_PG.pdf 2015."},{"key":"e_1_3_2_1_8_1","volume-title":"Carnegie Mellon Univ.","author":"Ausavarungnirun R.","year":"2017","unstructured":"R. Ausavarungnirun , \"Techniques for Shared Resource Management in Systems with Throughput Processors,\" Ph. D. dissertation , Carnegie Mellon Univ. , 2017 . R. Ausavarungnirun, \"Techniques for Shared Resource Management in Systems with Throughput Processors,\" Ph.D. dissertation, Carnegie Mellon Univ., 2017."},{"key":"e_1_3_2_1_9_1","volume-title":"Staged Memory Scheduling: Achieving High Performance and Scalability in Heterogeneous Systems,\" in ISCA","author":"Ausavarungnirun R.","year":"2012","unstructured":"R. Ausavarungnirun , K. Chang , L. Subramanian , G. Loh , and O. Mutlu , \" Staged Memory Scheduling: Achieving High Performance and Scalability in Heterogeneous Systems,\" in ISCA , 2012 . R. Ausavarungnirun, K. Chang, L. Subramanian, G. Loh, and O. Mutlu, \"Staged Memory Scheduling: Achieving High Performance and Scalability in Heterogeneous Systems,\" in ISCA, 2012."},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2015.38"},{"key":"e_1_3_2_1_12_1","volume-title":"Analyzing CUDA Workloads Using a Detailed GPU Simulator,\" in ISPASS","author":"Bakhoda A.","year":"2009","unstructured":"A. Bakhoda , G. Yuan , W. Fung , H. Wong , and T. Aamodt , \" Analyzing CUDA Workloads Using a Detailed GPU Simulator,\" in ISPASS , 2009 . A. Bakhoda, G. Yuan, W. Fung, H. Wong, and T. Aamodt, \"Analyzing CUDA Workloads Using a Detailed GPU Simulator,\" in ISPASS, 2009."},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1815970"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/2000064.2000101"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/2485922.2485943"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/2540708.2540741"},{"key":"e_1_3_2_1_17_1","volume-title":"Shared Last-level TLBs for Chip Multiprocessors,\" in HPCA","author":"Bhattacharjee A.","year":"2011","unstructured":"A. Bhattacharjee , D. Lustig , and M. Martonosi , \" Shared Last-level TLBs for Chip Multiprocessors,\" in HPCA , 2011 . A. Bhattacharjee, D. Lustig, and M. Martonosi, \"Shared Last-level TLBs for Chip Multiprocessors,\" in HPCA, 2011."},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2009.26"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/1736020.1736060"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/1941553.1941562"},{"key":"e_1_3_2_1_21_1","volume-title":"Low-Cost Inter-Linked Subarrays (LISA): Enabling Fast Inter-Subarray Data Movement in DRAM,\" in HPCA","author":"Chang K. K.","year":"2016","unstructured":"K. K. Chang , P. J. Nair , D. Lee , S. Ghose , M. K. Qureshi , and O. Mutlu , \" Low-Cost Inter-Linked Subarrays (LISA): Enabling Fast Inter-Subarray Data Movement in DRAM,\" in HPCA , 2016 . K. K. Chang, P. J. Nair, D. Lee, S. Ghose, M. K. Qureshi, and O. Mutlu, \"Low-Cost Inter-Linked Subarrays (LISA): Enabling Fast Inter-Subarray Data Movement in DRAM,\" in HPCA, 2016."},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2009.5306797"},{"key":"e_1_3_2_1_23_1","volume-title":"Supporting Address Translation for Accelerator-Centric Architectures,\" in HPCA","author":"Cong J.","year":"2017","unstructured":"J. Cong , Z. Fang , Y. Hao , and G. Reinman , \" Supporting Address Translation for Accelerator-Centric Architectures,\" in HPCA , 2017 . J. Cong, Z. Fang, Y. Hao, and G. Reinman, \"Supporting Address Translation for Accelerator-Centric Architectures,\" in HPCA, 2017."},{"key":"e_1_3_2_1_24_1","unstructured":"J. Corbet \"Transparent Hugepages \" https:\/\/lwn.net\/Articles\/359158\/ 2009.  J. Corbet \"Transparent Hugepages \" https:\/\/lwn.net\/Articles\/359158\/ 2009."},{"key":"e_1_3_2_1_25_1","unstructured":"Couchbase Inc. \"Often Overlooked Linux OS Tweaks \" http:\/\/blog.couchbase.com\/often-overlooked-linux-os-tweaks 2014.  Couchbase Inc. \"Often Overlooked Linux OS Tweaks \" http:\/\/blog.couchbase.com\/often-overlooked-linux-os-tweaks 2014."},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1145\/3037697.3037704"},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1145\/1735688.1735702"},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669150"},{"key":"e_1_3_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1815976"},{"key":"e_1_3_2_1_30_1","volume-title":"Supporting Superpages in Non-Contiguous Physical Memory,\" in HPCA","author":"Du Y.","year":"2015","unstructured":"Y. Du , M. Zhou , B. R. Childers , D. Moss\u00e9 , and R. Melhem , \" Supporting Superpages in Non-Contiguous Physical Memory,\" in HPCA , 2015 . Y. Du, M. Zhou, B. R. Childers, D. Moss\u00e9, and R. Melhem, \"Supporting Superpages in Non-Contiguous Physical Memory,\" in HPCA, 2015."},{"key":"e_1_3_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2008.44"},{"key":"e_1_3_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1109\/L-CA.2013.9"},{"key":"e_1_3_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.12"},{"key":"e_1_3_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2014.37"},{"key":"e_1_3_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2016.67"},{"key":"e_1_3_2_1_36_1","volume-title":"Large Pages May Be Harmful on NUMA Systems,\" in USENIX ATC","author":"Gaud F.","year":"2014","unstructured":"F. Gaud , B. Lepers , J. Decouchant , J. Funston , A. Fedorova , and V. Quema , \" Large Pages May Be Harmful on NUMA Systems,\" in USENIX ATC , 2014 . F. Gaud, B. Lepers, J. Decouchant, J. Funston, A. Fedorova, and V. Quema, \"Large Pages May Be Harmful on NUMA Systems,\" in USENIX ATC, 2014."},{"key":"e_1_3_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1145\/277650.277748"},{"key":"e_1_3_2_1_38_1","unstructured":"M. Gorman \"Huge Pages Part 2 (Interfaces) \" https:\/\/lwn.net\/Articles\/375096\/ 2010.  M. Gorman \"Huge Pages Part 2 (Interfaces) \" https:\/\/lwn.net\/Articles\/375096\/ 2010."},{"key":"e_1_3_2_1_39_1","doi-asserted-by":"publisher","DOI":"10.1145\/1375634.1375641"},{"key":"e_1_3_2_1_40_1","volume-title":"Performance Characteristics of Explicit Superpage Support,\" in WIOSCA","author":"Gorman M.","year":"2010","unstructured":"M. Gorman and P. Healy , \" Performance Characteristics of Explicit Superpage Support,\" in WIOSCA , 2010 . M. Gorman and P. Healy, \"Performance Characteristics of Explicit Superpage Support,\" in WIOSCA, 2010."},{"key":"e_1_3_2_1_41_1","unstructured":"Intel Corp. \"Introduction to Intel\u00ae Architecture \" http:\/\/www.intel.com\/content\/dam\/www\/public\/us\/en\/documents\/white-papers\/ia-introduction-basics-paper.pdf 2014.  Intel Corp. \"Introduction to Intel\u00ae Architecture \" http:\/\/www.intel.com\/content\/dam\/www\/public\/us\/en\/documents\/white-papers\/ia-introduction-basics-paper.pdf 2014."},{"key":"e_1_3_2_1_42_1","unstructured":"Intel Corp. \"Intel\u00ae 64 and IA-32 Architectures Optimization Reference Manual \" https:\/\/www.intel.com\/content\/dam\/www\/public\/us\/en\/documents\/manuals\/64-ia-32-architectures-optimization-manual.pdf 2016.  Intel Corp. \"Intel\u00ae 64 and IA-32 Architectures Optimization Reference Manual \" https:\/\/www.intel.com\/content\/dam\/www\/public\/us\/en\/documents\/manuals\/64-ia-32-architectures-optimization-manual.pdf 2016."},{"key":"e_1_3_2_1_43_1","unstructured":"Intel Corp. \"6th Generation Intel\u00ae Core\u2122 Processor Family Datasheet Vol. 1 \" http:\/\/www.intel.com\/content\/dam\/www\/public\/us\/en\/documents\/datasheets\/desktop-6th-gen-core-family-datasheet-vol-1.pdf 2017.  Intel Corp. \"6th Generation Intel\u00ae Core\u2122 Processor Family Datasheet Vol. 1 \" http:\/\/www.intel.com\/content\/dam\/www\/public\/us\/en\/documents\/datasheets\/desktop-6th-gen-core-family-datasheet-vol-1.pdf 2017."},{"key":"e_1_3_2_1_44_1","volume-title":"Pennsylvania State Univ.","author":"Jog A.","year":"2015","unstructured":"A. Jog , \"Design and Analysis of Scheduling Techniques for Throughput Processors,\" Ph. D. dissertation , Pennsylvania State Univ. , 2015 . A. Jog, \"Design and Analysis of Scheduling Techniques for Throughput Processors,\" Ph.D. dissertation, Pennsylvania State Univ., 2015."},{"key":"e_1_3_2_1_45_1","doi-asserted-by":"publisher","DOI":"10.1145\/2818950.2818979"},{"key":"e_1_3_2_1_46_1","doi-asserted-by":"publisher","DOI":"10.1145\/2485922.2485951"},{"key":"e_1_3_2_1_47_1","doi-asserted-by":"publisher","DOI":"10.1145\/2451116.2451158"},{"key":"e_1_3_2_1_48_1","doi-asserted-by":"publisher","DOI":"10.1145\/2896377.2901468"},{"key":"e_1_3_2_1_49_1","volume-title":"Going the Distance for TLB Prefetching: An Application-Driven Study,\" in ISCA","author":"Kandiraju G. B.","year":"2002","unstructured":"G. B. Kandiraju and A. Sivasubramaniam , \" Going the Distance for TLB Prefetching: An Application-Driven Study,\" in ISCA , 2002 . G. B. Kandiraju and A. Sivasubramaniam, \"Going the Distance for TLB Prefetching: An Application-Driven Study,\" in ISCA, 2002."},{"key":"e_1_3_2_1_50_1","doi-asserted-by":"publisher","DOI":"10.1145\/2749469.2749471"},{"key":"e_1_3_2_1_51_1","volume-title":"Energy-Efficient Address Translation,\" in HPCA","author":"Karakostas V.","year":"2016","unstructured":"V. Karakostas , J. Gandhi , A. Cristal , M. D. Hill , K. S. McKinley , M. Nemirovsky , M. M. Swift , and O. Unsal , \" Energy-Efficient Address Translation,\" in HPCA , 2016 . V. Karakostas, J. Gandhi, A. Cristal, M. D. Hill, K. S. McKinley, M. Nemirovsky, M. M. Swift, and O. Unsal, \"Energy-Efficient Address Translation,\" in HPCA, 2016."},{"key":"e_1_3_2_1_52_1","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2013.115"},{"key":"e_1_3_2_1_54_1","volume-title":"Managing GPU Concurrency in Heterogeneous Architectures,\" in MICRO","author":"Kay\u0131ran O.","year":"2014","unstructured":"O. Kay\u0131ran , N. Chidambaram , A. Jog , R. Ausavarungnirun , M. Kandemir , G. Loh , O. Mutlu , and C. Das , \" Managing GPU Concurrency in Heterogeneous Architectures,\" in MICRO , 2014 . O. Kay\u0131ran, N. Chidambaram, A. Jog, R. Ausavarungnirun, M. Kandemir, G. Loh, O. Mutlu, and C. Das, \"Managing GPU Concurrency in Heterogeneous Architectures,\" in MICRO, 2014."},{"key":"e_1_3_2_1_55_1","unstructured":"Khronos OpenCL Working Group \"The OpenCL Specification \" http:\/\/www.khronos.org\/registry\/cl\/specs\/opencl-1.0.29.pdf 2008.  Khronos OpenCL Working Group \"The OpenCL Specification \" http:\/\/www.khronos.org\/registry\/cl\/specs\/opencl-1.0.29.pdf 2008."},{"key":"e_1_3_2_1_56_1","volume-title":"ATLAS: A Scalable and High-Performance Scheduling Algorithm for Multiple Memory Controllers,\" in HPCA","author":"Kim Y.","year":"2010","unstructured":"Y. Kim , D. Han , O. Mutlu , and M. Harchol-Balter , \" ATLAS: A Scalable and High-Performance Scheduling Algorithm for Multiple Memory Controllers,\" in HPCA , 2010 . Y. Kim, D. Han, O. Mutlu, and M. Harchol-Balter, \"ATLAS: A Scalable and High-Performance Scheduling Algorithm for Multiple Memory Controllers,\" in HPCA, 2010."},{"key":"e_1_3_2_1_57_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2010.51"},{"key":"e_1_3_2_1_58_1","unstructured":"D. Kroft \"Lockup-Free Instruction Fetch\/Prefetch Cache Organization \" in ISCA 1981.   D. Kroft \"Lockup-Free Instruction Fetch\/Prefetch Cache Organization \" in ISCA 1981."},{"key":"e_1_3_2_1_59_1","volume-title":"Coordinated and Efficient Huge Page Management with Ingens,\" in OSDI","author":"Kwon Y.","year":"2016","unstructured":"Y. Kwon , H. Yu , S. Peter , C. J. Rossbach , and E. Witchel , \" Coordinated and Efficient Huge Page Management with Ingens,\" in OSDI , 2016 . Y. Kwon, H. Yu, S. Peter, C. J. Rossbach, and E. Witchel, \"Coordinated and Efficient Huge Page Management with Ingens,\" in OSDI, 2016."},{"key":"e_1_3_2_1_60_1","volume-title":"Advanced Micro Devices","author":"Kyriazis G.","year":"2012","unstructured":"G. Kyriazis , \"Heterogeneous System Architecture : A Technical Review,\" https:\/\/developer.amd.com\/wordpress\/media\/2012\/10\/hsa10.pdf , Advanced Micro Devices , Inc ., 2012 . G. Kyriazis, \"Heterogeneous System Architecture: A Technical Review,\" https:\/\/developer.amd.com\/wordpress\/media\/2012\/10\/hsa10.pdf, Advanced Micro Devices, Inc., 2012."},{"key":"e_1_3_2_1_61_1","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2015.51"},{"key":"e_1_3_2_1_62_1","doi-asserted-by":"publisher","DOI":"10.1145\/2628071.2628075"},{"key":"e_1_3_2_1_63_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2008.31"},{"key":"e_1_3_2_1_64_1","doi-asserted-by":"publisher","DOI":"10.1145\/2445572.2445574"},{"key":"e_1_3_2_1_65_1","unstructured":"Mark Mumy \"SAP IQ and Linux Hugepages\/Transparent Hugepages \" http:\/\/scn.sap.com\/people\/markmumy\/blog\/2014\/05\/22\/sap-iq-and-linux-hugepagestransparent-hugepages SAP SE 2014.  Mark Mumy \"SAP IQ and Linux Hugepages\/Transparent Hugepages \" http:\/\/scn.sap.com\/people\/markmumy\/blog\/2014\/05\/22\/sap-iq-and-linux-hugepagestransparent-hugepages SAP SE 2014."},{"key":"e_1_3_2_1_66_1","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2016.2549523"},{"key":"e_1_3_2_1_67_1","doi-asserted-by":"publisher","DOI":"10.1145\/2892242.2892258"},{"key":"e_1_3_2_1_68_1","unstructured":"Microsoft Corp. Large-Page Support in Windows https:\/\/msdn.microsoft.com\/en-us\/library\/windows\/desktop\/aa366720(v=vs.85).aspx.  Microsoft Corp. Large-Page Support in Windows https:\/\/msdn.microsoft.com\/en-us\/library\/windows\/desktop\/aa366720(v=vs.85).aspx."},{"key":"e_1_3_2_1_69_1","unstructured":"MongoDB Inc. \"Disable Transparent Huge Pages (THP) \" 2017.  MongoDB Inc. \"Disable Transparent Huge Pages (THP) \" 2017."},{"key":"e_1_3_2_1_70_1","doi-asserted-by":"publisher","DOI":"10.1145\/2155620.2155664"},{"key":"e_1_3_2_1_71_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.40"},{"key":"e_1_3_2_1_72_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.7"},{"key":"e_1_3_2_1_73_1","doi-asserted-by":"publisher","DOI":"10.1145\/2155620.2155656"},{"key":"e_1_3_2_1_74_1","volume-title":"Transparent Operating System Support for Superpages,\" in OSDI","author":"Navarro J.","year":"2002","unstructured":"J. Navarro , S. Iyer , P. Druschel , and A. Cox , \" Practical , Transparent Operating System Support for Superpages,\" in OSDI , 2002 . J. Navarro, S. Iyer, P. Druschel, and A. Cox, \"Practical, Transparent Operating System Support for Superpages,\" in OSDI, 2002."},{"key":"e_1_3_2_1_75_1","volume-title":"Yak: A High-Performance Big-Data-Friendly Garbage Collector,\" in OSDI","author":"Nguyen K.","year":"2016","unstructured":"K. Nguyen , L. Fang , G. Xu , B. Demsky , S. Lu , S. Alamian , and O. Mutlu , \" Yak: A High-Performance Big-Data-Friendly Garbage Collector,\" in OSDI , 2016 . K. Nguyen, L. Fang, G. Xu, B. Demsky, S. Lu, S. Alamian, and O. Mutlu, \"Yak: A High-Performance Big-Data-Friendly Garbage Collector,\" in OSDI, 2016."},{"key":"e_1_3_2_1_76_1","unstructured":"NVIDIA Corp. \"CUDA C\/C++ SDK Code Samples \" http:\/\/developer.nvidia.com\/cuda-cc-sdk-code-samples 2011.  NVIDIA Corp. \"CUDA C\/C++ SDK Code Samples \" http:\/\/developer.nvidia.com\/cuda-cc-sdk-code-samples 2011."},{"key":"e_1_3_2_1_77_1","volume-title":"Fermi,\" http:\/\/www.nvidia.com\/content\/pdf\/fermi_white_papers\/nvidia_fermi_compute_architecture_whitepaper.pdf","author":"NVIDIA Corp.","year":"2011","unstructured":"NVIDIA Corp. , \"NVIDIA's Next Generation CUDA Compute Architecture : Fermi,\" http:\/\/www.nvidia.com\/content\/pdf\/fermi_white_papers\/nvidia_fermi_compute_architecture_whitepaper.pdf , 2011 . NVIDIA Corp., \"NVIDIA's Next Generation CUDA Compute Architecture: Fermi,\" http:\/\/www.nvidia.com\/content\/pdf\/fermi_white_papers\/nvidia_fermi_compute_architecture_whitepaper.pdf, 2011."},{"key":"e_1_3_2_1_78_1","volume-title":"Kepler GK110,\" http:\/\/www.nvidia.com\/content\/PDF\/kepler\/NVIDIA-Kepler-GK110-Architecture-Whitepaper.pdf","author":"NVIDIA Corp.","year":"2012","unstructured":"NVIDIA Corp. , \"NVIDIA's Next Generation CUDA Compute Architecture : Kepler GK110,\" http:\/\/www.nvidia.com\/content\/PDF\/kepler\/NVIDIA-Kepler-GK110-Architecture-Whitepaper.pdf , 2012 . NVIDIA Corp., \"NVIDIA's Next Generation CUDA Compute Architecture: Kepler GK110,\" http:\/\/www.nvidia.com\/content\/PDF\/kepler\/NVIDIA-Kepler-GK110-Architecture-Whitepaper.pdf, 2012."},{"key":"e_1_3_2_1_79_1","unstructured":"NVIDIA Corp. \"NVIDIA GeForce GTX 750 Ti \" http:\/\/international.download.nvidia.com\/geforce-com\/international\/pdfs\/GeForce-GTX-750-Ti-Whitepaper.pdf 2014.  NVIDIA Corp. \"NVIDIA GeForce GTX 750 Ti \" http:\/\/international.download.nvidia.com\/geforce-com\/international\/pdfs\/GeForce-GTX-750-Ti-Whitepaper.pdf 2014."},{"key":"e_1_3_2_1_80_1","unstructured":"NVIDIA Corp. \"CUDA C Programming Guide \" http:\/\/docs.nvidia.com\/cuda\/cuda-c-programming-guide\/index.html 2015.  NVIDIA Corp. \"CUDA C Programming Guide \" http:\/\/docs.nvidia.com\/cuda\/cuda-c-programming-guide\/index.html 2015."},{"key":"e_1_3_2_1_81_1","unstructured":"NVIDIA Corp. \"NVIDIA RISC-V Story \" https:\/\/riscv.org\/wp-content\/uploads\/2016\/07\/Tue1100_Nvidia_RISCV_Story_V2.pdf 2016.  NVIDIA Corp. \"NVIDIA RISC-V Story \" https:\/\/riscv.org\/wp-content\/uploads\/2016\/07\/Tue1100_Nvidia_RISCV_Story_V2.pdf 2016."},{"key":"e_1_3_2_1_82_1","unstructured":"NVIDIA Corp. \"NVIDIA Tesla P100 \" https:\/\/images.nvidia.com\/content\/pdf\/tesla\/whitepaper\/pascal-architecture-whitepaper.pdf 2016.  NVIDIA Corp. \"NVIDIA Tesla P100 \" https:\/\/images.nvidia.com\/content\/pdf\/tesla\/whitepaper\/pascal-architecture-whitepaper.pdf 2016."},{"key":"e_1_3_2_1_83_1","unstructured":"NVIDIA Corp. \"NVIDIA GeForce GTX 1080 \" https:\/\/international.download.nvidia.com\/geforce-com\/international\/pdfs\/GeForce_GTX_1080_Whitepaper_FINAL.pdf 2017.  NVIDIA Corp. \"NVIDIA GeForce GTX 1080 \" https:\/\/international.download.nvidia.com\/geforce-com\/international\/pdfs\/GeForce_GTX_1080_Whitepaper_FINAL.pdf 2017."},{"key":"e_1_3_2_1_84_1","volume-title":"Prediction-Based Superpage-Friendly TLB Designs,\" in HPCA","author":"Papadopoulou M.-M.","year":"2015","unstructured":"M.-M. Papadopoulou , X. Tong , A. Seznec , and A. Moshovos , \" Prediction-Based Superpage-Friendly TLB Designs,\" in HPCA , 2015 . M.-M. Papadopoulou, X. Tong, A. Seznec, and A. Moshovos, \"Prediction-Based Superpage-Friendly TLB Designs,\" in HPCA, 2015."},{"key":"e_1_3_2_1_85_1","unstructured":"PCI-SIG \"PCI Express Base Specification Revision 3.1a \" 2015.  PCI-SIG \"PCI Express Base Specification Revision 3.1a \" 2015."},{"key":"e_1_3_2_1_86_1","volume-title":"A Case for Toggle-aware Compression for GPU Systems,\" in HPCA","author":"Pekhimenko G.","year":"2016","unstructured":"G. Pekhimenko , E. Bolotin , N. Vijaykumar , O. Mutlu , T. C. Mowry , and S. W. Keckler , \" A Case for Toggle-aware Compression for GPU Systems,\" in HPCA , 2016 . G. Pekhimenko, E. Bolotin, N. Vijaykumar, O. Mutlu, T. C. Mowry, and S. W. Keckler, \"A Case for Toggle-aware Compression for GPU Systems,\" in HPCA, 2016."},{"key":"e_1_3_2_1_87_1","unstructured":"Peter Zaitsev \"Why TokuDB Hates Transparent HugePages \" https:\/\/www.percona.com\/blog\/2014\/07\/23\/why-tokudb-hates-transparent-hugepages\/ Percona LLC 2014.  Peter Zaitsev \"Why TokuDB Hates Transparent HugePages \" https:\/\/www.percona.com\/blog\/2014\/07\/23\/why-tokudb-hates-transparent-hugepages\/ Percona LLC 2014."},{"key":"e_1_3_2_1_88_1","volume-title":"Increasing TLB Reach by Exploiting Clustering in Page Translations,\" in HPCA","author":"Pham B.","year":"2014","unstructured":"B. Pham , A. Bhattacharjee , Y. Eckert , and G. H. Loh , \" Increasing TLB Reach by Exploiting Clustering in Page Translations,\" in HPCA , 2014 . B. Pham, A. Bhattacharjee, Y. Eckert, and G. H. Loh, \"Increasing TLB Reach by Exploiting Clustering in Page Translations,\" in HPCA, 2014."},{"key":"e_1_3_2_1_89_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2012.32"},{"key":"e_1_3_2_1_90_1","doi-asserted-by":"publisher","DOI":"10.1145\/2830772.2830773"},{"key":"e_1_3_2_1_91_1","doi-asserted-by":"publisher","DOI":"10.1145\/2541940.2541942"},{"key":"e_1_3_2_1_92_1","volume-title":"Supporting x86--64 Address Translation for 100s of GPU Lanes,\" in HPCA","author":"Power J.","year":"2014","unstructured":"J. Power , M. D. Hill , and D. A. Wood , \" Supporting x86--64 Address Translation for 100s of GPU Lanes,\" in HPCA , 2014 . J. Power, M. D. Hill, and D. A. Wood, \"Supporting x86--64 Address Translation for 100s of GPU Lanes,\" in HPCA, 2014."},{"key":"e_1_3_2_1_93_1","unstructured":"Redis Labs \"Redis Latency Problems Troubleshooting \" http:\/\/redis.io\/topics\/latency.  Redis Labs \"Redis Latency Problems Troubleshooting \" http:\/\/redis.io\/topics\/latency."},{"key":"e_1_3_2_1_94_1","doi-asserted-by":"publisher","DOI":"10.1145\/339647.339668"},{"key":"e_1_3_2_1_95_1","volume-title":"dissertation","author":"Rogers T. G.","year":"2015","unstructured":"T. G. Rogers , \"Locality and Scheduling in the Massively Multithreaded Era,\" Ph. D. dissertation , Univ. of British Columbia , 2015 . T. G. Rogers, \"Locality and Scheduling in the Massively Multithreaded Era,\" Ph.D. dissertation, Univ. of British Columbia, 2015."},{"key":"e_1_3_2_1_96_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2012.16"},{"key":"e_1_3_2_1_97_1","doi-asserted-by":"publisher","DOI":"10.1145\/2517349.2522715"},{"key":"e_1_3_2_1_98_1","unstructured":"SAFARI Research Group \"Mosaic - GitHub Repository \" https:\/\/github.com\/CMU-SAFARI\/Mosaic\/.  SAFARI Research Group \"Mosaic - GitHub Repository \" https:\/\/github.com\/CMU-SAFARI\/Mosaic\/."},{"key":"e_1_3_2_1_99_1","unstructured":"SAFARI Research Group \"SAFARI Software Tools - GitHub Repository \" https:\/\/github.com\/CMU-SAFARI\/.  SAFARI Research Group \"SAFARI Software Tools - GitHub Repository \" https:\/\/github.com\/CMU-SAFARI\/."},{"key":"e_1_3_2_1_100_1","doi-asserted-by":"publisher","DOI":"10.1145\/339647.339666"},{"key":"e_1_3_2_1_101_1","volume-title":"RowClone: Fast and Energy-Efficient In-DRAM Bulk Data Copy and Initialization,\" in ISCA","author":"Seshadri V.","year":"2013","unstructured":"V. Seshadri , Y. Kim , C. Fallin , D. Lee , R. Ausavarungnirun , G. Pekhimenko , Y. Luo , O. Mutlu , P. B. Gibbons , M. A. Kozuch , and T. C. Mowry , \" RowClone: Fast and Energy-Efficient In-DRAM Bulk Data Copy and Initialization,\" in ISCA , 2013 . V. Seshadri, Y. Kim, C. Fallin, D. Lee, R. Ausavarungnirun, G. Pekhimenko, Y. Luo, O. Mutlu, P. B. Gibbons, M. A. Kozuch, and T. C. Mowry, \"RowClone: Fast and Energy-Efficient In-DRAM Bulk Data Copy and Initialization,\" in ISCA, 2013."},{"key":"e_1_3_2_1_102_1","volume-title":"Simple Operations in Memory to Reduce Data Movement,\" in Advances in Computers","author":"Seshadri V.","year":"2017","unstructured":"V. Seshadri and O. Mutlu , \" Simple Operations in Memory to Reduce Data Movement,\" in Advances in Computers , 2017 . V. Seshadri and O. Mutlu, \"Simple Operations in Memory to Reduce Data Movement,\" in Advances in Computers, 2017."},{"key":"e_1_3_2_1_103_1","volume-title":"Pentium Pro Processor System Architecture","author":"Shanley T.","year":"1996","unstructured":"T. Shanley , Pentium Pro Processor System Architecture , 1 st ed. Boston, MA, USA : Addison-Wesley Longman Publishing Co. , Inc., 1996 . T. Shanley, Pentium Pro Processor System Architecture, 1st ed. Boston, MA, USA: Addison-Wesley Longman Publishing Co., Inc., 1996.","edition":"1"},{"key":"e_1_3_2_1_104_1","volume-title":"ALPHA Architecture Reference Manual","author":"Sites R. L.","year":"1998","unstructured":"R. L. Sites and R. T. Witek , ALPHA Architecture Reference Manual . Boston, Oxford, Melbourne : Digital Press , 1998 . R. L. Sites and R. T. Witek, ALPHA Architecture Reference Manual. Boston, Oxford, Melbourne: Digital Press, 1998."},{"key":"e_1_3_2_1_105_1","doi-asserted-by":"crossref","unstructured":"B. Smith \"Architecture and Applications of the HEP Multiprocessor Computer System \" SPIE 1981.  B. Smith \"Architecture and Applications of the HEP Multiprocessor Computer System \" SPIE 1981.","DOI":"10.1117\/12.932535"},{"key":"e_1_3_2_1_106_1","volume-title":"Shared Resource MIMD Computer,\" in ICPP","author":"Smith B. J.","year":"1978","unstructured":"B. J. Smith , \" A Pipelined , Shared Resource MIMD Computer,\" in ICPP , 1978 . B. J. Smith, \"A Pipelined, Shared Resource MIMD Computer,\" in ICPP, 1978."},{"key":"e_1_3_2_1_107_1","unstructured":"Splunk Inc. \"Transparent Huge Memory Pages and Splunk Performance \" http:\/\/docs.splunk.com\/Documentation\/Splunk\/6.1.3\/ReleaseNotes\/SplunkandTHP 2013.  Splunk Inc. \"Transparent Huge Memory Pages and Splunk Performance \" http:\/\/docs.splunk.com\/Documentation\/Splunk\/6.1.3\/ReleaseNotes\/SplunkandTHP 2013."},{"key":"e_1_3_2_1_108_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2010.26"},{"key":"e_1_3_2_1_110_1","doi-asserted-by":"publisher","DOI":"10.1145\/2584665"},{"key":"e_1_3_2_1_111_1","doi-asserted-by":"publisher","DOI":"10.1145\/195473.195531"},{"key":"e_1_3_2_1_112_1","doi-asserted-by":"publisher","DOI":"10.1145\/1464039.1464045"},{"key":"e_1_3_2_1_113_1","volume-title":"Scott Foresman & Co","author":"Thornton J. E.","year":"1970","unstructured":"J. E. Thornton , Design of a Computer-The Control Data 6600 . Scott Foresman & Co , 1970 . J. E. Thornton, Design of a Computer-The Control Data 6600. Scott Foresman & Co, 1970."},{"key":"e_1_3_2_1_114_1","volume-title":"Observations and Opportunities in Architecting Shared Virtual Memory for Heterogeneous Systems,\" in ISPASS","author":"Vesely J.","year":"2016","unstructured":"J. Vesely , A. Basu , M. Oskin , G. H. Loh , and A. Bhattacharjee , \" Observations and Opportunities in Architecting Shared Virtual Memory for Heterogeneous Systems,\" in ISPASS , 2016 . J. Vesely, A. Basu, M. Oskin, G. H. Loh, and A. Bhattacharjee, \"Observations and Opportunities in Architecting Shared Virtual Memory for Heterogeneous Systems,\" in ISPASS, 2016."},{"key":"e_1_3_2_1_115_1","volume-title":"Zorua: A Holistic Approach to Resource Virtualization in GPUs,\" in MICRO","author":"Vijaykumar N.","year":"2016","unstructured":"N. Vijaykumar , K. Hsieh , G. Pekhimenko , S. Khan , A. Shrestha , S. Ghose , A. Jog , P. B. Gibbons , and O. Mutlu , \" Zorua: A Holistic Approach to Resource Virtualization in GPUs,\" in MICRO , 2016 . N. Vijaykumar, K. Hsieh, G. Pekhimenko, S. Khan, A. Shrestha, S. Ghose, A. Jog, P. B. Gibbons, and O. Mutlu, \"Zorua: A Holistic Approach to Resource Virtualization in GPUs,\" in MICRO, 2016."},{"key":"e_1_3_2_1_116_1","doi-asserted-by":"publisher","DOI":"10.1145\/2749469.2750399"},{"key":"e_1_3_2_1_117_1","volume-title":"Documentation: Configure Memory Management,\" https:\/\/docs.voltdb.com\/AdminGuide\/adminmemmgt.php.","unstructured":"VoltDB , Inc ., \"VoltDB Documentation: Configure Memory Management,\" https:\/\/docs.voltdb.com\/AdminGuide\/adminmemmgt.php. VoltDB, Inc., \"VoltDB Documentation: Configure Memory Management,\" https:\/\/docs.voltdb.com\/AdminGuide\/adminmemmgt.php."},{"key":"e_1_3_2_1_118_1","volume-title":"Towards High Performance Paged Memory for GPUs,\" in HPCA","author":"Zheng T.","year":"2016","unstructured":"T. Zheng , D. Nellans , A. Zulfiqar , M. Stephenson , and S. W. Keckler , \" Towards High Performance Paged Memory for GPUs,\" in HPCA , 2016 . T. Zheng, D. Nellans, A. Zulfiqar, M. Stephenson, and S. W. Keckler, \"Towards High Performance Paged Memory for GPUs,\" in HPCA, 2016."},{"key":"e_1_3_2_1_119_1","volume-title":"Controller for a Synchronous DRAM That Maximizes Throughput by Allowing Memory Requests and Commands to Be Issued Out of Order,\" US Patent No. 5,630,096","author":"Zuravleff W. K.","year":"1997","unstructured":"W. K. Zuravleff and T. Robinson , \" Controller for a Synchronous DRAM That Maximizes Throughput by Allowing Memory Requests and Commands to Be Issued Out of Order,\" US Patent No. 5,630,096 , 1997 . W. K. Zuravleff and T. Robinson, \"Controller for a Synchronous DRAM That Maximizes Throughput by Allowing Memory Requests and Commands to Be Issued Out of Order,\" US Patent No. 5,630,096, 1997."}],"event":{"name":"MICRO-50: The 50th Annual IEEE\/ACM International Symposium on Microarchitecture","location":"Cambridge Massachusetts","acronym":"MICRO-50","sponsor":["SIGMICRO ACM Special Interest Group on Microarchitectural Research and Processing","IEEE-CS\\DATC IEEE Computer Society"]},"container-title":["Proceedings of the 50th Annual IEEE\/ACM International Symposium on Microarchitecture"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3123939.3123975","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3123939.3123975","content-type":"application\/pdf","content-version":"vor","intended-application":"syndication"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3123939.3123975","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T03:30:31Z","timestamp":1750217431000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3123939.3123975"}},"subtitle":["a GPU memory manager with application-transparent support for multiple page sizes"],"short-title":[],"issued":{"date-parts":[[2017,10,14]]},"references-count":116,"alternative-id":["10.1145\/3123939.3123975","10.1145\/3123939"],"URL":"https:\/\/doi.org\/10.1145\/3123939.3123975","relation":{},"subject":[],"published":{"date-parts":[[2017,10,14]]},"assertion":[{"value":"2017-10-14","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}