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Code Optim."],"published-print":{"date-parts":[[2017,9,30]]},"abstract":"<jats:p>\n            Interapplication interference at shared main memory slows down different applications differently. A few slowdown estimation models have been proposed to provide predictable performance by quantifying memory interference, but they have relatively low accuracy. Thus, we propose a more accurate slowdown estimation model called\n            <jats:italic>SEM<\/jats:italic>\n            at main memory. First, SEM unifies the slowdown estimation model by measuring IPC directly. Second, SEM uses the per-bank structure to monitor memory interference and improves estimation accuracy by considering write interference, row-buffer interference, and data bus interference. The evaluation results show that SEM has significantly lower slowdown estimation error (4.06%) compared to STFM (30.15%) and MISE (10.1%).\n          <\/jats:p>","DOI":"10.1145\/3124451","type":"journal-article","created":{"date-parts":[[2017,8,24]],"date-time":"2017-08-24T11:49:04Z","timestamp":1503575344000},"page":"1-26","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":1,"title":["Providing Predictable Performance via a Slowdown Estimation Model"],"prefix":"10.1145","volume":"14","author":[{"given":"Dongliang","family":"Xiong","sequence":"first","affiliation":[{"name":"Zhejiang University, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kai","family":"Huang","sequence":"additional","affiliation":[{"name":"Zhejiang University, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xiaowen","family":"Jiang","sequence":"additional","affiliation":[{"name":"Zhejiang University, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xiaolang","family":"Yan","sequence":"additional","affiliation":[{"name":"Zhejiang University, China"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2017,8,22]]},"reference":[{"key":"e_1_2_1_1_1","volume-title":"Proceedings of HPCA 201","author":"Kai-Wei Chang Kevin","year":"2014","unstructured":"Kevin Kai-Wei Chang , Donghyuk Lee , Zeshan Chishti , Alaa R. Alameldeen , Chris Wiklerson , Yoongu Kim , and Onur Mutlu . 2014 . Improving DRAM performance by parallelizing refreshes with accesses . In Proceedings of HPCA 201 Kevin Kai-Wei Chang, Donghyuk Lee, Zeshan Chishti, Alaa R. Alameldeen, Chris Wiklerson, Yoongu Kim, and Onur Mutlu. 2014. Improving DRAM performance by parallelizing refreshes with accesses. In Proceedings of HPCA 201"},{"key":"e_1_2_1_2_1","volume-title":"USIMM: The Utah Simulated Memory Module.","author":"Chatterjee Niladrish","year":"2012","unstructured":"Niladrish Chatterjee , Rajeev Balasubramonian , Manjunath Shevgoor , Seth H. Pugsley , Aniruddha N. Udipi , Ali Shafiee , Kshitij Sudan , Manu Awasthi , and Zeshan Chishti . 2012 . USIMM: The Utah Simulated Memory Module. Available at http:\/\/www.cs.utah.edu\/&sim;rajeev\/jwac12\/. Niladrish Chatterjee, Rajeev Balasubramonian, Manjunath Shevgoor, Seth H. Pugsley, Aniruddha N. Udipi, Ali Shafiee, Kshitij Sudan, Manu Awasthi, and Zeshan Chishti. 2012. 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