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Although several mixed-criticality multi-core scheduling approaches have been proposed, currently there are few implementations on hardware that demonstrate efficient resource utilization and the ability to bound interference on shared resources. To address this necessity, we develop a mixed-criticality runtime environment on the Kalray MPPA-256 Andey many-core platform. The runtime environment implements a scheduling policy based on adaptive temporal partitioning. We develop models, methods and implementation principles to implement the necessary scheduling primitives, to achieve high platform utilization and to perform a compositional worst-case execution time analysis. The bounds account for scheduling overheads and for the inter-task interference on the platform\u2019s shared memory. Using realistic benchmarks from avionics and signal processing, we validate the correctness and tightness of the bounds and demonstrate a high platform utilization.<\/jats:p>","DOI":"10.1145\/3126533","type":"journal-article","created":{"date-parts":[[2017,9,27]],"date-time":"2017-09-27T12:33:53Z","timestamp":1506515633000},"page":"1-21","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":8,"title":["Implementation of Partitioned Mixed-Criticality Scheduling on a Multi-Core Platform"],"prefix":"10.1145","volume":"16","author":[{"given":"Roman","family":"Tr\u00fcb","sequence":"first","affiliation":[{"name":"Computer Engineering and Networks Laboratory, ETH Zurich, Switzerland"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Georgia","family":"Giannopoulou","sequence":"additional","affiliation":[{"name":"Computer Engineering and Networks Laboratory, ETH Zurich, Switzerland"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Andreas","family":"Tretter","sequence":"additional","affiliation":[{"name":"Computer Engineering and Networks Laboratory, ETH Zurich, Switzerland"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Lothar","family":"Thiele","sequence":"additional","affiliation":[{"name":"Computer Engineering and Networks Laboratory, ETH Zurich, Switzerland"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2017,9,27]]},"reference":[{"key":"e_1_2_1_1_1","unstructured":"AbsInt. 2015. aiT Worst-Case Execution time Analyzers. https:\/\/www.absint.com\/ait\/. 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