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In this work, we propose a security-aware systematic design approach which explores the design space, given a system-level application description, by generating potential architecture configurations of execution platform nodes that are interconnected using a NoC. We then perform automated security analysis to check the generated configurations against designer-specified security constraints. Following the analysis, we use an automated architecture configuration refinement process to generate a list of security additions that are inserted into the initial configuration so that the security constraints are satisfied. By performing this refinement on several candidate configuration options, we can explore the trade-off between resource cost and security. In this paper, we illustrate the proposed approach using a Smart Home Control System application.<\/jats:p>","DOI":"10.1145\/3126553","type":"journal-article","created":{"date-parts":[[2017,9,27]],"date-time":"2017-09-27T12:33:53Z","timestamp":1506515633000},"page":"1-20","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":5,"title":["An Automated Security-Aware Approach for Design of Embedded Systems on MPSoC"],"prefix":"10.1145","volume":"16","author":[{"given":"Benjamin","family":"Tan","sequence":"first","affiliation":[{"name":"University of Auckland, New Zealand"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Morteza","family":"Biglari-Abhari","sequence":"additional","affiliation":[{"name":"University of Auckland, New Zealand"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Zoran","family":"Salcic","sequence":"additional","affiliation":[{"name":"University of Auckland, New Zealand"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2017,9,27]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/1873548.1873550"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/2744769.2744922"},{"volume-title":"2016 29th Symposium on Integrated Circuits and Systems Design (SBCCI). 1--6.","author":"Fernandes R.","key":"e_1_2_1_3_1","unstructured":"R. Fernandes , C. Marcon , R. Cataldo , J. Silveira , G. Sigl , and J. Sepulveda . 2016. A security aware routing approach for NoC-based MPSoCs . In 2016 29th Symposium on Integrated Circuits and Systems Design (SBCCI). 1--6. R. Fernandes, C. Marcon, R. Cataldo, J. Silveira, G. Sigl, and J. Sepulveda. 2016. A security aware routing approach for NoC-based MPSoCs. In 2016 29th Symposium on Integrated Circuits and Systems Design (SBCCI). 1--6."},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2008.69"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2448684"},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/INA-OCMC.2015.9"},{"key":"e_1_2_1_7_1","doi-asserted-by":"crossref","unstructured":"E. Kang. 2016. Design Space Exploration for Security. In 2016 IEEE Cybersecurity Development (SecDev). 30--36.  E. Kang. 2016. Design Space Exploration for Security. In 2016 IEEE Cybersecurity Development (SecDev). 30--36.","DOI":"10.1109\/SecDev.2016.017"},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/356989.357005"},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/TETC.2014.2348182"},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2010.2053856"},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/DSD.2015.100"},{"volume-title":"Optimizing Latencies and Customizing NoC of Time-Predictable Heterogeneous Multi-Core Processor. In IEEE 10th International Symposium on Embedded Multicore\/Many-core Systems-on-Chip (MCSoC-16)","author":"Salcic Z.","key":"e_1_2_1_13_1","unstructured":"Z. Salcic , M. Nadeem , H. Park , and J. Teich . 2016 . Optimizing Latencies and Customizing NoC of Time-Predictable Heterogeneous Multi-Core Processor. In IEEE 10th International Symposium on Embedded Multicore\/Many-core Systems-on-Chip (MCSoC-16) . Z. Salcic, M. Nadeem, H. Park, and J. Teich. 2016. Optimizing Latencies and Customizing NoC of Time-Predictable Heterogeneous Multi-Core Processor. In IEEE 10th International Symposium on Embedded Multicore\/Many-core Systems-on-Chip (MCSoC-16)."},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-37300-8_2"},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSREW.2014.29"},{"key":"e_1_2_1_16_1","first-page":"45","article-title":"Eternal War in Memory. Security 8 Privacy","volume":"12","author":"Szekeres L.","year":"2014","unstructured":"L. Szekeres , M. Payer , L. T. Wei , and R. Sekar . 2014 . Eternal War in Memory. Security 8 Privacy , IEEE 12 , 3 (2014), 45 -- 53 . L. Szekeres, M. Payer, L. T. Wei, and R. Sekar. 2014. Eternal War in Memory. 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