{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,24]],"date-time":"2025-10-24T16:41:59Z","timestamp":1761324119291,"version":"3.41.0"},"reference-count":34,"publisher":"Association for Computing Machinery (ACM)","issue":"5s","license":[{"start":{"date-parts":[[2017,9,27]],"date-time":"2017-09-27T00:00:00Z","timestamp":1506470400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"Shenzhen Science and Technology Foundation","award":["JCYJ20150525092941059, JCYJ20150529164656096, and JCYJ20150731160834611"],"award-info":[{"award-number":["JCYJ20150525092941059, JCYJ20150529164656096, and JCYJ20150731160834611"]}]},{"name":"Natural Science Foundation of SZU","award":["803-000026080154 and 827-000073"],"award-info":[{"award-number":["803-000026080154 and 827-000073"]}]},{"name":"State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences","award":["CARCH201608"],"award-info":[{"award-number":["CARCH201608"]}]},{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["61502309 and U1301252"],"award-info":[{"award-number":["61502309 and U1301252"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"name":"China 863","award":["2015AA015305"],"award-info":[{"award-number":["2015AA015305"]}]},{"DOI":"10.13039\/501100003453","name":"Guangdong Natural Science Foundation","doi-asserted-by":"crossref","award":["2014A030310269, 2014A030313553 and 2016A030313045"],"award-info":[{"award-number":["2014A030310269, 2014A030313553 and 2016A030313045"]}],"id":[{"id":"10.13039\/501100003453","id-type":"DOI","asserted-by":"crossref"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Embed. Comput. Syst."],"published-print":{"date-parts":[[2017,10,31]]},"abstract":"<jats:p>Three-dimensional (3D) flash memory is an emerging memory technology that enables a number of improvements to conventional planar NAND flash memory, including larger capacity, less program disturbance, and lower access latency. In contrast to conventional planar flash memory, 3D flash memory adopts charge-trapping mechanism. NAND strings punch through multiple stacked layers to form the three-dimensional infrastructure. However, the etching processes for NAND strings are unable to produce perfectly vertical features, especially on the scale of 20 nanometers or less. The process variation will cause uneven distribution of electrons, which poses a threat to the integrity of data stored in flash.<\/jats:p>\n          <jats:p>\n            This paper present\n            <jats:italic>P-Alloc<\/jats:italic>\n            , a process-variation tolerant reliability management strategy for 3D charge-trapping flash memory. P-Alloc offers both hardware and software support to allocate data to the 3D flash in the presence of process variation. P-Alloc predicts the state of a physical page, i.e., the basic unit for each write or read operation in flash memory, and tries to assign critical data to more reliable pages. A hardware-based voltage threshold compensation scheme is also proposed to further reduce the faults. We demonstrate the viability of the proposed scheme using a variety of realistic workloads. Our extensive evaluations show that, P-Alloc significantly enhances the reliability and reduces the access latency compared to the baseline scheme.\n          <\/jats:p>","DOI":"10.1145\/3126554","type":"journal-article","created":{"date-parts":[[2017,9,27]],"date-time":"2017-09-27T12:33:53Z","timestamp":1506515633000},"page":"1-19","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":17,"title":["P-Alloc"],"prefix":"10.1145","volume":"16","author":[{"given":"Yi","family":"Wang","sequence":"first","affiliation":[{"name":"Shenzhen University, Shenzhen, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Lisha","family":"Dong","sequence":"additional","affiliation":[{"name":"Shenzhen University, Shenzhen, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Rui","family":"Mao","sequence":"additional","affiliation":[{"name":"Shenzhen University, Shenzhen, China"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2017,9,27]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/2968456.2968475"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.5555\/2561828.2561912"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.5555\/2840819.2840886"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2016.2595572"},{"key":"e_1_2_1_5_1","first-page":"1","volume-title":"Proceedings of the Ninth IEEE\/ACM\/IFIP International Conference on Hardware\/Software Codesign and System Synthesis (CODES+ISSS\u201913)","author":"Chen R.","unstructured":"R. Chen , Y. Wang , and Z. Shao . 2013. DHeating: Dispersed heating repair for self-healing NAND flash memory . In Proceedings of the Ninth IEEE\/ACM\/IFIP International Conference on Hardware\/Software Codesign and System Synthesis (CODES+ISSS\u201913) . pages 7: 1 -- 7 :10. R. Chen, Y. Wang, and Z. Shao. 2013. DHeating: Dispersed heating repair for self-healing NAND flash memory. In Proceedings of the Ninth IEEE\/ACM\/IFIP International Conference on Hardware\/Software Codesign and System Synthesis (CODES+ISSS\u201913). pages 7:1--7:10."},{"volume-title":"2015 IEEE Asian Solid-State Circuits Conference (A-SSCC\u201915)","author":"Choi S.","key":"e_1_2_1_6_1","unstructured":"S. Choi , K. Park , M. Passerini , H. Park , D. Kim , C. Kim , K. Park , and J. Kim . 2015. A cell current compensation scheme for 3D NAND FLASH memory . In 2015 IEEE Asian Solid-State Circuits Conference (A-SSCC\u201915) . 1--4. S. Choi, K. Park, M. Passerini, H. Park, D. Kim, C. Kim, K. Park, and J. Kim. 2015. A cell current compensation scheme for 3D NAND FLASH memory. In 2015 IEEE Asian Solid-State Circuits Conference (A-SSCC\u201915). 1--4."},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2008.925922"},{"key":"e_1_2_1_8_1","first-page":"1","article-title":"A block-level log-block management scheme for MLC NAND flash memory storage systems","volume":"99","author":"Guan Y.","year":"2017","unstructured":"Y. Guan , G. Wang , C. Ma , R. Chen , Y. Wang , and Z. Shao . 2017 . A block-level log-block management scheme for MLC NAND flash memory storage systems . IEEE Trans. Comput. PP , 99 (2017), 1 -- 1 . Y. Guan, G. Wang, C. Ma, R. Chen, Y. Wang, and Z. Shao. 2017. A block-level log-block management scheme for MLC NAND flash memory storage systems. IEEE Trans. Comput. PP, 99 (2017), 1--1.","journal-title":"IEEE Trans. Comput. PP"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/2968456.2968465"},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/2744769.2744843"},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2013.2277653"},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2014.2318716"},{"volume-title":"2010 IEEE International Memory Workshop. 1--4.","author":"Hsiao Y. H.","key":"e_1_2_1_13_1","unstructured":"Y. H. Hsiao , H. T. Lue , T. H. Hsu , K. Y. Hsieh , and C. Y. Lu . 2010. A critical examination of 3D stackable NAND flash memory architectures by simulation study of the scaling capability . In 2010 IEEE International Memory Workshop. 1--4. Y. H. Hsiao, H. T. Lue, T. H. Hsu, K. Y. Hsieh, and C. Y. Lu. 2010. A critical examination of 3D stackable NAND flash memory architectures by simulation study of the scaling capability. In 2010 IEEE International Memory Workshop. 1--4."},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2016.7573386"},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2015.2413841"},{"volume-title":"2011 Symposium on VLSI Technology - Digest of Technical Papers. 68--69","author":"Hung C. H.","key":"e_1_2_1_16_1","unstructured":"C. H. Hung , H. T. Lue , K. P. Chang , C. P. Chen , Y. H. Hsiao , S. H. Chen , Y. H. Shih , K. Y. Hsieh , M. Yang , J. Lee , S. Y. Wang , T. Yang , K. C. Chen , and C. Y. Lu . 2011. A highly scalable vertical gate (VG) 3D NAND Flash with robust program disturb immunity using a novel PN diode decoding structure . In 2011 Symposium on VLSI Technology - Digest of Technical Papers. 68--69 . C. H. Hung, H. T. Lue, K. P. Chang, C. P. Chen, Y. H. Hsiao, S. H. Chen, Y. H. Shih, K. Y. Hsieh, M. Yang, J. Lee, S. Y. Wang, T. Yang, K. C. Chen, and C. Y. Lu. 2011. A highly scalable vertical gate (VG) 3D NAND Flash with robust program disturb immunity using a novel PN diode decoding structure. In 2011 Symposium on VLSI Technology - Digest of Technical Papers. 68--69."},{"key":"e_1_2_1_17_1","volume-title":"Proceedings of the 2009 Symposium on VLSI Technology (VLSIT\u201909)","author":"Jang J.","year":"2009","unstructured":"J. Jang , H.-S. Kim , W. Cho , H. Cho , J. Kim , S.-I. Shim , Y. Jang , J.-H. Jeong , B.-K. Son , D.-W. Kim , K., J.-J. Shim , J.-S. Lim , K.-H. Kim , S.-Y. Yi , J.-Y. Lim , D. Chung , H.-C. Moon , S. Hwang , J.-W. Lee , Y.-H. Son , U.-I. Chung , and W.-S. Lee . 2009 . Vertical cell array using TCAT (Terabit Cell array transistor) technology for ultra high density NAND flash memory . In Proceedings of the 2009 Symposium on VLSI Technology (VLSIT\u201909) . 192--193. J. Jang, H.-S. Kim, W. Cho, H. Cho, J. Kim, S.-I. Shim, Y. Jang, J.-H. Jeong, B.-K. Son, D.-W. Kim, K., J.-J. Shim, J.-S. Lim, K.-H. Kim, S.-Y. Yi, J.-Y. Lim, D. Chung, H.-C. Moon, S. Hwang, J.-W. Lee, Y.-H. Son, U.-I. Chung, and W.-S. Lee. 2009. Vertical cell array using TCAT (Terabit Cell array transistor) technology for ultra high density NAND flash memory. In Proceedings of the 2009 Symposium on VLSI Technology (VLSIT\u201909). 192--193."},{"volume-title":"Proceedings of the 2009 Symposium on VLSI Technology (VLSIT\u201909)","author":"Katsumata R.","key":"e_1_2_1_18_1","unstructured":"R. Katsumata , M. Kito , Y. Fukuzumi , M. Kido , H. Tanaka , Y. Komori , M. Ishiduki , J. Matsunami , T. Fujiwara , Y. Nagata , L. Zhang , Y. Iwata , R. Kirisawa , H. Aochi , and A. Nitayama . 2009. Pipe-shaped BiCS flash memory with 16 stacked layers and multi-level-cell operation for ultra high density storage devices . In Proceedings of the 2009 Symposium on VLSI Technology (VLSIT\u201909) . 136--137. R. Katsumata, M. Kito, Y. Fukuzumi, M. Kido, H. Tanaka, Y. Komori, M. Ishiduki, J. Matsunami, T. Fujiwara, Y. Nagata, L. Zhang, Y. Iwata, R. Kirisawa, H. Aochi, and A. Nitayama. 2009. Pipe-shaped BiCS flash memory with 16 stacked layers and multi-level-cell operation for ultra high density storage devices. In Proceedings of the 2009 Symposium on VLSI Technology (VLSIT\u201909). 136--137."},{"volume-title":"Proceedings of the 2009 Symposium on VLSI Technology (VLSIT\u201909)","author":"Kim J.","key":"e_1_2_1_19_1","unstructured":"J. Kim , A. J. Hong , S.M. Kim , E. B. Song , J. H. Park , J. Han , S. Choi , D. Jang , J.-T. Moon , and K. L. Wang . 2009. Novel vertical-stacked-array-transistor (VSAT) for ultra-high-density and cost-effective NAND flash memory devices and SSD (solid state drive) . In Proceedings of the 2009 Symposium on VLSI Technology (VLSIT\u201909) . 186--187. J. Kim, A. J. Hong, S.M. Kim, E. B. Song, J. H. Park, J. Han, S. Choi, D. Jang, J.-T. Moon, and K. L. Wang. 2009. Novel vertical-stacked-array-transistor (VSAT) for ultra-high-density and cost-effective NAND flash memory devices and SSD (solid state drive). In Proceedings of the 2009 Symposium on VLSI Technology (VLSIT\u201909). 186--187."},{"volume-title":"Proceedings of the 2009 Symposium on VLSI Technology (VLSIT\u201909)","author":"Kim W.","key":"e_1_2_1_20_1","unstructured":"W. Kim , S. Choi , J. Sung , T. Lee , C. Park , H. Ko , J. Jung , I. Yoo , and Y. Park . 2009. Multi-layered vertical gate NAND flash overcoming stacking limit for terabit density storage . In Proceedings of the 2009 Symposium on VLSI Technology (VLSIT\u201909) . 188--189. W. Kim, S. Choi, J. Sung, T. Lee, C. Park, H. Ko, J. Jung, I. Yoo, and Y. Park. 2009. Multi-layered vertical gate NAND flash overcoming stacking limit for terabit density storage. In Proceedings of the 2009 Symposium on VLSI Technology (VLSIT\u201909). 188--189."},{"volume-title":"2016 IEEE International Electron Devices Meeting (IEDM\u201916)","author":"Lee J.","key":"e_1_2_1_21_1","unstructured":"J. Lee , J. Jang , J. Lim , Y. G. Shin , K. Lee , and E. Jung . 2016. A new ruler on the storage market: 3D-NAND flash for high-density memory and its technology evolutions and challenges on the future . In 2016 IEEE International Electron Devices Meeting (IEDM\u201916) . 11.2.1--11.2.4. J. Lee, J. Jang, J. Lim, Y. G. Shin, K. Lee, and E. Jung. 2016. A new ruler on the storage market: 3D-NAND flash for high-density memory and its technology evolutions and challenges on the future. In 2016 IEEE International Electron Devices Meeting (IEDM\u201916). 11.2.1--11.2.4."},{"key":"e_1_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/2905054"},{"key":"e_1_2_1_23_1","volume-title":"2009 IEEE International Electron Devices Meeting (IEDM\u201909)","author":"Liu R.","year":"2009","unstructured":"R. Liu , H. T. Lue , K. C. Chen , and C.-Y. Lu . 2009 . Reliability of barrier engineered charge trapping devices for sub-30nm NAND flash . In 2009 IEEE International Electron Devices Meeting (IEDM\u201909) . 1--4. R. Liu, H. T. Lue, K. C. Chen, and C.-Y. Lu. 2009. Reliability of barrier engineered charge trapping devices for sub-30nm NAND flash. In 2009 IEEE International Electron Devices Meeting (IEDM\u201909). 1--4."},{"key":"e_1_2_1_24_1","volume-title":"Future prospects of NAND flash memory technology--the evolution from floating gate to charge trapping to 3D stacking.Journal of Nanoscience and Nanotechnology 12, 10","author":"Lu C. Y.","year":"2012","unstructured":"C. Y. Lu . 2012. Future prospects of NAND flash memory technology--the evolution from floating gate to charge trapping to 3D stacking.Journal of Nanoscience and Nanotechnology 12, 10 ( 2012 ), 7604--18. C. Y. Lu. 2012. Future prospects of NAND flash memory technology--the evolution from floating gate to charge trapping to 3D stacking.Journal of Nanoscience and Nanotechnology 12, 10 (2012), 7604--18."},{"key":"e_1_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1145\/2699866"},{"key":"e_1_2_1_26_1","unstructured":"N. Ramaswamy and G. S. Sandhu. 2015. Charge-trap based memory. US Patent US 9 029 256 B2 (2015).  N. Ramaswamy and G. S. Sandhu. 2015. Charge-trap based memory. US Patent US 9 029 256 B2 (2015)."},{"key":"e_1_2_1_27_1","first-page":"11","article-title":"A reliability-aware address mapping strategy for NAND flash memory storage systems","volume":"33","author":"Wang Y.","year":"2014","unstructured":"Y. Wang , M. Huang , Z. Shao , H. Chan , L. A. D. Bathen , and N. D. Dutt . 2014 . A reliability-aware address mapping strategy for NAND flash memory storage systems . IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 33 , 11 (Nov 2014), 1623--1631. Y. Wang, M. Huang, Z. Shao, H. Chan, L. A. D. Bathen, and N. D. Dutt. 2014. A reliability-aware address mapping strategy for NAND flash memory storage systems. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 33, 11 (Nov 2014), 1623--1631.","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"key":"e_1_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2013.2288687"},{"key":"e_1_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.sysarc.2016.07.003"},{"key":"e_1_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1145\/2934583.2934638"},{"volume-title":"2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC). 572--577","author":"Wang Y.","key":"e_1_2_1_31_1","unstructured":"Y. Wang , M. Zhang , and J. Yang . 2017. Temperature-aware data allocation strategy for 3D charge-trap flash memory . In 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC). 572--577 . Y. Wang, M. Zhang, and J. Yang. 2017. Temperature-aware data allocation strategy for 3D charge-trap flash memory. In 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC). 572--577."},{"key":"e_1_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1145\/2744769.2744929"},{"key":"e_1_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1145\/2593069.2593124"},{"key":"e_1_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1145\/2992782"}],"container-title":["ACM Transactions on Embedded Computing Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3126554","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3126554","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T19:05:02Z","timestamp":1750273502000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3126554"}},"subtitle":["Process-Variation Tolerant Reliability Management for 3D Charge-Trapping Flash Memory"],"short-title":[],"issued":{"date-parts":[[2017,9,27]]},"references-count":34,"journal-issue":{"issue":"5s","published-print":{"date-parts":[[2017,10,31]]}},"alternative-id":["10.1145\/3126554"],"URL":"https:\/\/doi.org\/10.1145\/3126554","relation":{},"ISSN":["1539-9087","1558-3465"],"issn-type":[{"type":"print","value":"1539-9087"},{"type":"electronic","value":"1558-3465"}],"subject":[],"published":{"date-parts":[[2017,9,27]]},"assertion":[{"value":"2017-03-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2017-06-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2017-09-27","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}