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Syst."],"published-print":{"date-parts":[[2017,10,31]]},"abstract":"<jats:p>The energy efficiency of digital architectures is tightly linked to the voltage level (Vdd) at which they operate. Aggressive voltage scaling is therefore mandatory when ultra-low power processing is required. Nonetheless, the lowest admissible Vdd is often bounded by reliability concerns, especially since static and dynamic non-idealities are exacerbated in the near-threshold region, imposing costly guard-bands to guarantee correctness under worst-case conditions. A striking alternative, explored in this paper, waives the requirement for unconditional correctness, undergoing more relaxed constraints. First, after a run-time failure, processing correctly resumes at a later point in time. Second, failures induce a limited Quality-of-Service (QoS) degradation. We focus our investigation on the practical scenario of embedded bio-signal analysis, a domain in which energy efficiency is key, while applications are inherently error-tolerant to a certain degree. Targeting a domain-specific multi-core platform, we present a study of the impact of inexactness on application-visible errors. Then, we introduce a novel methodology to manage them, which requires minimal hardware resources and a negligible energy overhead. Experimental evidence show that, by tolerating 900 errors\/hour, the resulting inexact platform can achieve an efficiency increase of up to 24%, with a QoS degradation of less than 3%.<\/jats:p>","DOI":"10.1145\/3126565","type":"journal-article","created":{"date-parts":[[2017,9,27]],"date-time":"2017-09-27T12:33:53Z","timestamp":1506515633000},"page":"1-19","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":7,"title":["An Inexact Ultra-low Power Bio-signal Processing Architecture With Lightweight Error Recovery"],"prefix":"10.1145","volume":"16","author":[{"given":"Soumya","family":"Basu","sequence":"first","affiliation":[{"name":"Swiss Federal Institute of Technology Lausanne (EPFL), Switzerland"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Loris","family":"Duch","sequence":"additional","affiliation":[{"name":"Swiss Federal Institute of Technology Lausanne (EPFL), Switzerland"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Rub\u00c9n","family":"Braojos","sequence":"additional","affiliation":[{"name":"Swiss Federal Institute of Technology Lausanne (EPFL), Switzerland"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Giovanni","family":"Ansaloni","sequence":"additional","affiliation":[{"name":"Universit\u00e0 della Svizzera Italiana (USI), Switzerland"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Laura","family":"Pozzi","sequence":"additional","affiliation":[{"name":"Universit\u00e0 della Svizzera Italiana (USI), Switzerland"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"David","family":"Atienza","sequence":"additional","affiliation":[{"name":"Swiss Federal Institute of Technology Lausanne (EPFL), Switzerland"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2017,9,27]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.comnet.2010.05.003"},{"key":"e_1_2_1_2_1","volume-title":"Solid-State Circuits Conference Digest of Technical Papers (ISSCC)","author":"Ashouei M.","year":"2011","unstructured":"M. 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