{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T04:36:01Z","timestamp":1750221361136,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":16,"publisher":"ACM","license":[{"start":{"date-parts":[[2017,10,19]],"date-time":"2017-10-19T00:00:00Z","timestamp":1508371200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2017,10,19]]},"DOI":"10.1145\/3130265.3130316","type":"proceedings-article","created":{"date-parts":[[2018,1,23]],"date-time":"2018-01-23T13:26:49Z","timestamp":1516714009000},"page":"16-22","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":1,"title":["Prototyping dynamic task migration on heterogeneous reconfigurable systems"],"prefix":"10.1145","author":[{"given":"Arief","family":"Wicaksana","sequence":"first","affiliation":[{"name":"Univ. Grenoble Alpes, Grenoble, France"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Alban","family":"Bourge","sequence":"additional","affiliation":[{"name":"Univ. Grenoble Alpes, Grenoble, France"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Olivier","family":"Muller","sequence":"additional","affiliation":[{"name":"Univ. Grenoble Alpes, Grenoble, France"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Arif","family":"Sasongko","sequence":"additional","affiliation":[{"name":"Institut Teknologi Bandung, Bandung, Indonesia"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Fr\u00e9d\u00e9ric","family":"Rousseau","sequence":"additional","affiliation":[{"name":"Univ. Grenoble Alpes, Grenoble, France"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2017,10,19]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.5555\/1131481.1131488"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/2996199"},{"key":"e_1_3_2_1_3_1","volume-title":"2015 International Conference on. IEEE, 183--192","author":"El-Antably Ashaf","year":"2015","unstructured":"Ashaf El-Antably , Olivier Gruber , Frederic Rousseau , and Nicolas Fournel . 2015 . Transparent and Portable Agent Based Task Migration for Data-Flow Applications on Multi-Tiled Architectures. In Hardware\/Software Codesign and System Synthesis (CODES+ ISSS) , 2015 International Conference on. IEEE, 183--192 . Ashaf El-Antably, Olivier Gruber, Frederic Rousseau, and Nicolas Fournel. 2015. Transparent and Portable Agent Based Task Migration for Data-Flow Applications on Multi-Tiled Architectures. In Hardware\/Software Codesign and System Synthesis (CODES+ ISSS), 2015 International Conference on. IEEE, 183--192."},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/1460361.1460365"},{"key":"e_1_3_2_1_5_1","volume-title":"Circuits and Systems, 2008. ISCAS 2008. IEEE International Symposium on. IEEE, 1192--1195","author":"Hara Yuko","year":"2008","unstructured":"Yuko Hara , Hiroyuki Tomiyama , Shinya Honda , Hiroaki Takada , and Katsuya Ishii . 2008 . CHStone: a Benchmark Program Suite for Practical C-based High-Level Synthesis . In Circuits and Systems, 2008. ISCAS 2008. IEEE International Symposium on. IEEE, 1192--1195 . Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada, and Katsuya Ishii. 2008. CHStone: a Benchmark Program Suite for Practical C-based High-Level Synthesis. In Circuits and Systems, 2008. ISCAS 2008. IEEE International Symposium on. IEEE, 1192--1195."},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/LES.2012.2193660"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/3039902.3039913"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/1216919.1216950"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/1142980.1142986"},{"key":"e_1_3_2_1_10_1","volume-title":"Architecture Virtualization for Run-Time Hardware Multithreading on Field Programmable Gate Arrays. In International Symposium on Applied Reconfigurable Computing. Springer, 167--178","author":"Metzner Michael","year":"2015","unstructured":"Michael Metzner , Jesus A Lizarraga , and Christophe Bobda . 2015 . Architecture Virtualization for Run-Time Hardware Multithreading on Field Programmable Gate Arrays. In International Symposium on Applied Reconfigurable Computing. Springer, 167--178 . Michael Metzner, Jesus A Lizarraga, and Christophe Bobda. 2015. Architecture Virtualization for Run-Time Hardware Multithreading on Field Programmable Gate Arrays. In International Symposium on Applied Reconfigurable Computing. Springer, 167--178."},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2013.13"},{"key":"e_1_3_2_1_12_1","volume-title":"Jean-Christophe Le Lann, and Lo\u00cfc Lagadec","author":"Najem Mohamad","year":"2017","unstructured":"Mohamad Najem , Th\u00e9otime Bollengier , Jean-Christophe Le Lann, and Lo\u00cfc Lagadec . 2017 . Extended Overlay Architectures For Heterogeneous FPGA Cluster Management. Journal of Systems Architecture ( 2017). Mohamad Najem, Th\u00e9otime Bollengier, Jean-Christophe Le Lann, and Lo\u00cfc Lagadec. 2017. Extended Overlay Architectures For Heterogeneous FPGA Cluster Management. Journal of Systems Architecture (2017)."},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.sysarc.2013.10.002"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2015.42"},{"key":"e_1_3_2_1_15_1","volume-title":"Multitasking on FPGA Coprocessors. In International Workshop on Field Programmable Logic and Applications (FPL). Springer, 121--130","author":"Simmler Harald","year":"2000","unstructured":"Harald Simmler , L Levinson , and Reinhard M\u00e4nner . 2000 . Multitasking on FPGA Coprocessors. In International Workshop on Field Programmable Logic and Applications (FPL). Springer, 121--130 . Harald Simmler, L Levinson, and Reinhard M\u00e4nner. 2000. Multitasking on FPGA Coprocessors. In International Workshop on Field Programmable Logic and Applications (FPL). Springer, 121--130."},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/IDT.2016.7843005"}],"event":{"name":"ESWEEK'17: THIRTEENTH EMBEDDED SYSTEM WEEK","sponsor":["SIGBED ACM Special Interest Group on Embedded Systems","SIGDA ACM Special Interest Group on Design Automation","IEEE CAS","IEEE Council on Electronic Design Automation (CEDA)","SIGMICRO ACM Special Interest Group on Microarchitectural Research and Processing"],"location":"Seoul South Korea","acronym":"ESWEEK'17"},"container-title":["Proceedings of the 28th International Symposium on Rapid System Prototyping: Shortening the Path from Specification to Prototype"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3130265.3130316","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3130265.3130316","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T02:26:16Z","timestamp":1750213576000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3130265.3130316"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,10,19]]},"references-count":16,"alternative-id":["10.1145\/3130265.3130316","10.1145\/3130265"],"URL":"https:\/\/doi.org\/10.1145\/3130265.3130316","relation":{},"subject":[],"published":{"date-parts":[[2017,10,19]]},"assertion":[{"value":"2017-10-19","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}