{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,9,29]],"date-time":"2026-09-29T10:09:40Z","timestamp":1790676580516,"version":"4.1.0"},"publisher-location":"New York, NY, USA","reference-count":21,"publisher":"ACM","license":[{"start":{"date-parts":[[2017,10,19]],"date-time":"2017-10-19T00:00:00Z","timestamp":1508371200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2017,10,19]]},"DOI":"10.1145\/3130265.3130322","type":"proceedings-article","created":{"date-parts":[[2018,1,23]],"date-time":"2018-01-23T13:26:49Z","timestamp":1516714009000},"page":"43-49","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":5,"title":["Software platform dedicated for in-memory computing circuit evaluation"],"prefix":"10.1145","author":[{"given":"Maha","family":"Kooli","sequence":"first","affiliation":[{"name":"Grenoble Alpes, Grenoble"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Henri-Pierre","family":"Charles","sequence":"additional","affiliation":[{"name":"Grenoble Alpes, Grenoble"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Cl\u00e9ment","family":"Touzet","sequence":"additional","affiliation":[{"name":"Grenoble Alpes, Grenoble"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Bastien","family":"Giraud","sequence":"additional","affiliation":[{"name":"Grenoble Alpes, Grenoble"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Jean-Philippe","family":"No\u00ebl","sequence":"additional","affiliation":[{"name":"Grenoble Alpes, Grenoble"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2017,10,19]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"{n. d.}. ARM: Architecture for the Digital World Cortex-M7 Processor. www.arm.com\/products\/processors\/cortex-m\/cortex-m7-processor.php. ({n. d.}).  {n. d.}. ARM: Architecture for the Digital World Cortex-M7 Processor. www.arm.com\/products\/processors\/cortex-m\/cortex-m7-processor.php. ({n. d.})."},{"key":"e_1_3_2_1_2_1","unstructured":"{n. d.}. clang: a C language family frontend for LLVM. www.clang.llvm.org\/. ({n. d.}).  {n. d.}. clang: a C language family frontend for LLVM. www.clang.llvm.org\/. ({n. d.})."},{"key":"e_1_3_2_1_3_1","unstructured":"{n. d.}. LLVM Language Reference Manual. www.llvm.org\/docs\/LangRef.htmlinteger-type. ({n. d.}).  {n. d.}. LLVM Language Reference Manual. www.llvm.org\/docs\/LangRef.htmlinteger-type. ({n. d.})."},{"key":"e_1_3_2_1_4_1","volume-title":"Compute Caches. In IEEE International Symposium on High Performance Computer Architecture (HPCA). 481--492","author":"Shaizeen","unstructured":"Shaizeen Aga et al. 2017 . Compute Caches. In IEEE International Symposium on High Performance Computer Architecture (HPCA). 481--492 . Shaizeen Aga et al. 2017. Compute Caches. In IEEE International Symposium on High Performance Computer Architecture (HPCA). 481--492."},{"key":"e_1_3_2_1_5_1","volume-title":"IEEE International Conference on Rebooting Computing (ICRC). 1--8.","author":"Can Kaya","unstructured":"Kaya Can Akyel et al. 2016. DRC 2: Dynamically Reconfigurable Computing Circuit based on memory architecture . In IEEE International Conference on Rebooting Computing (ICRC). 1--8. Kaya Can Akyel et al. 2016. DRC 2: Dynamically Reconfigurable Computing Circuit based on memory architecture. In IEEE International Conference on Rebooting Computing (ICRC). 1--8."},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/2.375174"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2012.6242474"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2515510"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2661838"},{"key":"e_1_3_2_1_10_1","volume-title":"Symposium on VLSI Technology. IEEE, T222--T223","author":"V","unstructured":"V Joshi et al. 2017. Low-variation SRAM bitcells in 22nm FDSOI technology . In Symposium on VLSI Technology. IEEE, T222--T223 . V Joshi et al. 2017. Low-variation SRAM bitcells in 22nm FDSOI technology. In Symposium on VLSI Technology. IEEE, T222--T223."},{"key":"e_1_3_2_1_11_1","article-title":"Motion Detection Algorithm","volume":"1","author":"Kohli Kamna","year":"2013","unstructured":"Kamna Kohli and Jatinder Pal Singh . 2013 . Motion Detection Algorithm . International Journal of Computer Science & Applications (TIJCSA) 1 , 12 (2013). Kamna Kohli and Jatinder Pal Singh. 2013. Motion Detection Algorithm. International Journal of Computer Science & Applications (TIJCSA) 1, 12 (2013).","journal-title":"International Journal of Computer Science & Applications (TIJCSA)"},{"key":"e_1_3_2_1_12_1","unstructured":"Maha Kooli. 2016. Analysing and Supporting the Reliability Decision-making Process in Computing Systems with a Reliability Evaluation Framework. Theses. Universit\u00e9 Montpellier.  Maha Kooli. 2016. Analysing and Supporting the Reliability Decision-making Process in Computing Systems with a Reliability Evaluation Framework. Theses. Universit\u00e9 Montpellier."},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.5555\/977395.977673"},{"key":"e_1_3_2_1_14_1","volume-title":"Workshop on Accelerator-Enabled Algorithms and Applications in Bioinformatics","author":"Dominique","unstructured":"Dominique Lavenier et al. 2016. DNA Mapping using Processor-in-Memory Architecture . In Workshop on Accelerator-Enabled Algorithms and Applications in Bioinformatics . Shenzhen, China. Dominique Lavenier et al. 2016. DNA Mapping using Processor-in-Memory Architecture. In Workshop on Accelerator-Enabled Algorithms and Applications in Bioinformatics. Shenzhen, China."},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/2897937.2898064"},{"key":"e_1_3_2_1_16_1","volume-title":"Proceedings of the Conference on Design, Automation and Test in Europe. European Design and Automation Association, 433--435","author":"Shoun","unstructured":"Shoun Matsunaga et al. 2009. MTJ-based nonvolatile logic-in-memory circuit, future prospects and issues . In Proceedings of the Conference on Design, Automation and Test in Europe. European Design and Automation Association, 433--435 . Shoun Matsunaga et al. 2009. MTJ-based nonvolatile logic-in-memory circuit, future prospects and issues. In Proceedings of the Conference on Design, Automation and Test in Europe. European Design and Automation Association, 433--435."},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/40.592312"},{"key":"e_1_3_2_1_18_1","volume-title":"IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS). 190--200","author":"Seth","unstructured":"Seth H Pugsley et al. 2014. NDC: Analyzing the impact of 3D-stacked memory + logic devices on MapReduce workloads . In IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS). 190--200 . Seth H Pugsley et al. 2014. NDC: Analyzing the impact of 3D-stacked memory + logic devices on MapReduce workloads. In IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS). 190--200."},{"key":"e_1_3_2_1_19_1","unstructured":"Bruce Schneier. 2007. Applied cryptography: protocols algorithms and source code in C. john wiley & sons.  Bruce Schneier. 2007. Applied cryptography: protocols algorithms and source code in C. john wiley & sons."},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/TIFS.2016.2576903"},{"key":"e_1_3_2_1_21_1","unstructured":"Qiuling Zhu et al. 2013. A 3D-stacked logic-in-memory accelerator for application-specific data intensive computing. In IEEE International 3D Systems Integration Conference (3DIC). 1--7.  Qiuling Zhu et al. 2013. A 3D-stacked logic-in-memory accelerator for application-specific data intensive computing. In IEEE International 3D Systems Integration Conference (3DIC). 1--7."}],"event":{"name":"ESWEEK'17: THIRTEENTH EMBEDDED SYSTEM WEEK","location":"Seoul South Korea","acronym":"ESWEEK'17","sponsor":["SIGBED ACM Special Interest Group on Embedded Systems","SIGDA ACM Special Interest Group on Design Automation","IEEE CAS","IEEE Council on Electronic Design Automation (CEDA)","SIGMICRO ACM Special Interest Group on Microarchitectural Research and Processing"]},"container-title":["Proceedings of the 28th International Symposium on Rapid System Prototyping: Shortening the Path from Specification to Prototype"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3130265.3130322","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3130265.3130322","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T02:26:17Z","timestamp":1750213577000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3130265.3130322"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,10,19]]},"references-count":21,"alternative-id":["10.1145\/3130265.3130322","10.1145\/3130265"],"URL":"https:\/\/doi.org\/10.1145\/3130265.3130322","relation":{},"subject":[],"published":{"date-parts":[[2017,10,19]]},"assertion":[{"value":"2017-10-19","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}