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The main goal is to devise a task mapping which meets a predefined reliability threshold considering a minimized performance degradation. The proposed approach uses a majority-voting replication technique to fulfill error-masking capability. A quantitative reliability model is also proposed for the platform. Our platform is a homogenous many-core architecture with mesh-based interconnection using traditional deterministic XY routing algorithm. Our iterative approach is applicable to an unlimited number of system fault types. All parts of the platform, including cores, links, and routers, are assumed to be prone to failures. We used the MNLP optimization technique to find the optimal mapping of the presented task graph. Experimental results show that our suggested task mappings not only comply with predefined reliability thresholds but also achieve notable time complexity reduction with respect to exhaustive space exploration.<\/jats:p>","DOI":"10.1145\/3131273","type":"journal-article","created":{"date-parts":[[2017,12,6]],"date-time":"2017-12-06T21:23:15Z","timestamp":1512595395000},"page":"1-31","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":12,"title":["A Majority-Based Reliability-Aware Task Mapping in High-Performance Homogenous NoC Architectures"],"prefix":"10.1145","volume":"17","author":[{"given":"Alireza","family":"Namazi","sequence":"first","affiliation":[{"name":"School of Electrical and Computer, University of Tehran, Iran"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Meisam","family":"Abdollahi","sequence":"additional","affiliation":[{"name":"School of Electrical and Computer, University of Tehran, Iran"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Saeed","family":"Safari","sequence":"additional","affiliation":[{"name":"School of Electrical and Computer, University of Tehran, Iran"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Siamak","family":"Mohammadi","sequence":"additional","affiliation":[{"name":"School of Electrical and Computer, University of Tehran, Iran"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2017,12,6]]},"reference":[{"key":"e_1_2_1_1_1","first-page":"21","article-title":"Survey of network on chip (noc) architectures 8 contributions","volume":"3","author":"Agarwal A.","year":"2009","journal-title":"Journal of Engineering, Computing and Architecture"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.jpdc.2013.02.009"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/MCAS.2004.1330747"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2012.6187577"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/1132952.1132953"},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/DFT.2010.11"},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2012.226"},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/1278480.1278667"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/RTSS.2008.23"},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/VLSISOC.2009.6041333"},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISPA.2014.11"},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2010.2058873"},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2014.2315203"},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228480"},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/12.53599"},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1007\/BF01660031"},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/12.762534"},{"key":"e_1_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/1978802.1978814"},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.5626\/JCSE.2013.7.1.67"},{"key":"e_1_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/71.473515"},{"key":"e_1_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1109\/CCGrid.2013.62"},{"key":"e_1_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2013.6509555"},{"key":"e_1_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2011.190"},{"key":"e_1_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2012.6187578"},{"key":"e_1_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1109\/TDSC.2008.50"},{"key":"e_1_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.jpdc.2008.11.002"},{"key":"e_1_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1145\/2039370.2039409"},{"key":"e_1_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.5555\/1494646.1495128"},{"key":"e_1_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1002\/cpe.1763"},{"key":"e_1_2_1_30_1","volume-title":"Proceedings of the 2009 Design, Automation 8 Test in Europe Conference 8 Exhibition. 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