{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,25]],"date-time":"2026-06-25T02:02:41Z","timestamp":1782352961017,"version":"3.54.5"},"reference-count":40,"publisher":"Association for Computing Machinery (ACM)","issue":"2","license":[{"start":{"date-parts":[[2017,10,5]],"date-time":"2017-10-05T00:00:00Z","timestamp":1507161600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"National 863 Programs","award":["2015AA015304"],"award-info":[{"award-number":["2015AA015304"]}]},{"DOI":"10.13039\/501100001809","name":"NSFC","doi-asserted-by":"crossref","award":["61402059, 61472052 and 61572411"],"award-info":[{"award-number":["61402059, 61472052 and 61572411"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"crossref"}]},{"DOI":"10.13039\/501100012226","name":"Fundamental Research Funds for the Central Universities","doi-asserted-by":"crossref","award":["106112016CDJZR185512"],"award-info":[{"award-number":["106112016CDJZR185512"]}],"id":[{"id":"10.13039\/501100012226","id-type":"DOI","asserted-by":"crossref"}]},{"name":"Huawei Innovation Research Program"},{"name":"Fundamental Research Funds for Graduate Scientific Research and Innovation Foundation of Chongqing, China","award":["CYB14043"],"award-info":[{"award-number":["CYB14043"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Des. Autom. Electron. Syst."],"published-print":{"date-parts":[[2018,3,31]]},"abstract":"<jats:p>\n            Solid state drives (SSDs) are normally constructed with a number of parallel-accessible flash chips, where host I\/O requests are processed in parallel. In addition, there are many internal activities in SSDs, such as garbage collection and wear leveling induced read, write, and erase operations, to solve the issues of inability of in-place updates and limited lifetime. When internal activities are triggered on a chip, the chip will be blocked. Our preliminary studies on several workloads show that when internal activities are frequently triggered, the host I\/O performance will be significantly impacted because of the\n            <jats:italic>access conflict<\/jats:italic>\n            between them. In this work, in order to improve the access conflict induced performance degradation, a novel\n            <jats:italic>access conflict<\/jats:italic>\n            minimization scheme is proposed. The basic idea of the scheme is motivated by an interesting observation in SSDs: several chips are idle when other chips are busy with internal activities and host I\/O requests. Based on this observation, we propose to schedule internal activities induced operations for minimized access conflict by exploiting the idleness of the multiple chips of SSDs. This approach is realized by two steps: First, read internal activities accessed data to the controller; second, by exploiting the idle chips during internal activities, write internal activities accessed data back to these idle chips. With this scheme, the internal activities can be processed with minimized access conflict to the host requests. Simulation results show that the proposed approach significantly reduces the access conflict, and in turn leads to a significant performance improvement of SSDs.\n          <\/jats:p>","DOI":"10.1145\/3131850","type":"journal-article","created":{"date-parts":[[2017,10,6]],"date-time":"2017-10-06T12:48:39Z","timestamp":1507294119000},"page":"1-29","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":22,"title":["Exploiting Chip Idleness for Minimizing Garbage Collection\u2014Induced Chip Access Conflict on SSDs"],"prefix":"10.1145","volume":"23","author":[{"given":"Congming","family":"Gao","sequence":"first","affiliation":[{"name":"College of Computer Science, Chongqing University, Chongqing, People's Republic of China, Chongqing, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Liang","family":"Shi","sequence":"additional","affiliation":[{"name":"College of Computer Science, Chongqing University, Chongqing, People's Republic of China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Yejia","family":"Di","sequence":"additional","affiliation":[{"name":"College of Computer Science, Chongqing University, Chongqing, People's Republic of China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Qiao","family":"Li","sequence":"additional","affiliation":[{"name":"College of Computer Science, Chongqing University, Chongqing, People's Republic of China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Chun Jason","family":"Xue","sequence":"additional","affiliation":[{"name":"Department of Computer Science, City University of Hong Kong, Kowloon, Hong Kong"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Kaijie","family":"Wu","sequence":"additional","affiliation":[{"name":"College of Computer Science, Chongqing University, Chongqing, People\u2019s Republic of China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Edwin","family":"Sha","sequence":"additional","affiliation":[{"name":"College of Computer Science, Chongqing University, Chongqing, People\u2019s Republic of China"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2017,10,5]]},"reference":[{"key":"e_1_2_1_1_1","unstructured":"Nitin Agrawal Vijayan Prabhakaran Ted Wobber John D. Davis Mark Manasse and Rina Panigrahy. 2008. Design tradeoffs for SSD performance. In ATC. 57--70.  Nitin Agrawal Vijayan Prabhakaran Ted Wobber John D. Davis Mark Manasse and Rina Panigrahy. 2008. Design tradeoffs for SSD performance. In ATC. 57--70."},{"key":"e_1_2_1_2_1","volume-title":"Ganger","author":"Bucy John S.","year":"2008","unstructured":"John S. Bucy , Jiri Schindler , Steven W. Schlosser , and Gregory R . Ganger . 2008 . The disksim simulation environment version 4.0 reference manual. Parallel Data Laboratory ( 2008), 26. John S. Bucy, Jiri Schindler, Steven W. Schlosser, and Gregory R. Ganger. 2008. The disksim simulation environment version 4.0 reference manual. Parallel Data Laboratory (2008), 26."},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/1027794.1027801"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/2544375.2544383"},{"key":"e_1_2_1_5_1","doi-asserted-by":"crossref","unstructured":"Yuan-Hao Chang Jen-Wei Hsieh and Tei-Wei Kuo. 2007. Endurance enhancement of flash-memory storage systems: An efficient static wear leveling design. In DAC. 212--217.  Yuan-Hao Chang Jen-Wei Hsieh and Tei-Wei Kuo. 2007. Endurance enhancement of flash-memory storage systems: An efficient static wear leveling design. In DAC. 212--217.","DOI":"10.1109\/DAC.2007.375155"},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/1555349.1555371"},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2011.5749735"},{"key":"e_1_2_1_8_1","volume-title":"FAST","volume":"11","author":"Chen Feng","year":"2011","unstructured":"Feng Chen , Tian Luo , and Xiaodong Zhang . 2011 b. CAFTL: A content-aware flash translation layer enhancing the lifespan of flash memory based solid state drives . In FAST , Vol. 11 . Feng Chen, Tian Luo, and Xiaodong Zhang. 2011b. CAFTL: A content-aware flash translation layer enhancing the lifespan of flash memory based solid state drives. In FAST, Vol. 11."},{"key":"e_1_2_1_9_1","volume-title":"Automation & Test in Europe Conference & Exhibition. EDA Consortium, 1209--1212","author":"Chen Fu-Hsin","year":"2015","unstructured":"Fu-Hsin Chen , Ming-Chang Yang , Yuan-Hao Chang , and Tei-Wei Kuo . 2015 . PWL: A progressive wear leveling to minimize data migration overheads for NAND flash devices. In 2015 Design , Automation & Test in Europe Conference & Exhibition. EDA Consortium, 1209--1212 . Fu-Hsin Chen, Ming-Chang Yang, Yuan-Hao Chang, and Tei-Wei Kuo. 2015. PWL: A progressive wear leveling to minimize data migration overheads for NAND flash devices. In 2015 Design, Automation & Test in Europe Conference & Exhibition. EDA Consortium, 1209--1212."},{"key":"e_1_2_1_10_1","first-page":"1","article-title":"SAC: Rethinking the cache replacement policy for SSD-based storage systems","volume":"13","author":"Chen Zhiguang","year":"2012","unstructured":"Zhiguang Chen , Nong Xiao , and Fang Liu . 2012 . SAC: Rethinking the cache replacement policy for SSD-based storage systems . In SYSTOR. 13 : 1 -- 13 :12. Zhiguang Chen, Nong Xiao, and Fang Liu. 2012. SAC: Rethinking the cache replacement policy for SSD-based storage systems. In SYSTOR. 13:1--13:12.","journal-title":"SYSTOR."},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1002\/(SICI)1097-024X(199903)29:3%3C267::AID-SPE233%3E3.0.CO;2-T"},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/1555815.1555790"},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/3037697.3037728"},{"key":"e_1_2_1_14_1","unstructured":"Fusionio. 2016. NVMe SSDs. https:\/\/www.micron.com\/products\/solid-state-storage\/bus-interfaces\/nvme-ssds#\/.  Fusionio. 2016. NVMe SSDs. https:\/\/www.micron.com\/products\/solid-state-storage\/bus-interfaces\/nvme-ssds#\/."},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2017.2693281"},{"key":"e_1_2_1_16_1","volume-title":"Kaijie Wu, and Edwin H.-M. Sha.","author":"Gao Congming","year":"2014","unstructured":"Congming Gao , Liang Shi , Mengying Zhao , Chun Jason Xue , Kaijie Wu, and Edwin H.-M. Sha. 2014 . Exploiting parallelism in I\/O scheduling for access conflict minimization in flash-based solid state drives. In MSST. 1--11. Congming Gao, Liang Shi, Mengying Zhao, Chun Jason Xue, Kaijie Wu, and Edwin H.-M. Sha. 2014. Exploiting parallelism in I\/O scheduling for access conflict minimization in flash-based solid state drives. In MSST. 1--11."},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/1508244.1508271"},{"key":"e_1_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2014.2308199"},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/1995896.1995912"},{"key":"e_1_2_1_20_1","unstructured":"Myoungsoo Jung and Mahmut Kandemir. 2012. An evaluation of different page allocation strategies on high-speed SSDs. In Hotstorage. 9--9.  Myoungsoo Jung and Mahmut Kandemir. 2012. An evaluation of different page allocation strategies on high-speed SSDs. In Hotstorage. 9--9."},{"key":"e_1_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-35170-9_9"},{"key":"e_1_2_1_22_1","doi-asserted-by":"crossref","unstructured":"Myoungsoo Jung Ellis H. Wilson III and Mahmut Kandemir. 2012b. Physically addressed queueing (PAQ): Improving parallelism in solid state disks. In ISCA. 404--415.  Myoungsoo Jung Ellis H. Wilson III and Mahmut Kandemir. 2012b. Physically addressed queueing (PAQ): Improving parallelism in solid state disks. In ISCA. 404--415.","DOI":"10.1145\/2366231.2337206"},{"key":"e_1_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1145\/2588555.2595632"},{"key":"e_1_2_1_24_1","first-page":"1","article-title":"BPLRU: A buffer management scheme for improving random writes in flash storage","volume":"8","author":"Kim Hyojun","year":"2008","unstructured":"Hyojun Kim and Seongjun Ahn . 2008 . BPLRU: A buffer management scheme for improving random writes in flash storage . In FAST , Vol. 8. 1 -- 14 . Hyojun Kim and Seongjun Ahn. 2008. BPLRU: A buffer management scheme for improving random writes in flash storage. In FAST, Vol. 8. 1--14.","journal-title":"FAST"},{"key":"e_1_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2012.2227479"},{"key":"e_1_2_1_26_1","volume-title":"-M. Sha","author":"Li Qiao","year":"2016","unstructured":"Qiao Li , Liang Shi , Chun J. Xue , Kaijie Wu , Cheng Ji , Qingfeng Zhuge , and Edwin H . -M. Sha . 2016 . Access characteristic guided read and write cost regulation for performance improvement on flash memory. In FAST. 125. Qiao Li, Liang Shi, Chun J. Xue, Kaijie Wu, Cheng Ji, Qingfeng Zhuge, and Edwin H.-M. Sha. 2016. Access characteristic guided read and write cost regulation for performance improvement on flash memory. In FAST. 125."},{"key":"e_1_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2015.7357145"},{"key":"e_1_2_1_28_1","volume-title":"SFS: Random write considered harmful in solid state drives. In FAST. 12--12.","author":"Min Changwoo","year":"2012","unstructured":"Changwoo Min , Kangnyeon Kim , Hyunjin Cho , Sang-Won Lee , and Young Ik Eom . 2012 . SFS: Random write considered harmful in solid state drives. In FAST. 12--12. Changwoo Min, Kangnyeon Kim, Hyunjin Cho, Sang-Won Lee, and Young Ik Eom. 2012. SFS: Random write considered harmful in solid state drives. In FAST. 12--12."},{"key":"e_1_2_1_29_1","volume-title":"Du","author":"Murugan Muthukumar","year":"2011","unstructured":"Muthukumar Murugan and David H. C , Du . 2011 . Rejuvenator : A static wear leveling algorithm for NAND flash memory with minimized overhead. In MSST. IEEE , 1--12. Muthukumar Murugan and David H. C, Du. 2011. Rejuvenator: A static wear leveling algorithm for NAND flash memory with minimized overhead. In MSST. IEEE, 1--12."},{"key":"e_1_2_1_30_1","volume-title":"Sameh Elnikety, and Antony Rowstron.","author":"Narayanan Dushyanth","year":"2009","unstructured":"Dushyanth Narayanan , Eno Thereska , Austin Donnelly , Sameh Elnikety, and Antony Rowstron. 2009 . Migrating server storage to SSDs: Analysis of tradeoffs. In EuroSys . 145--158. Dushyanth Narayanan, Eno Thereska, Austin Donnelly, Sameh Elnikety, and Antony Rowstron. 2009. Migrating server storage to SSDs: Analysis of tradeoffs. In EuroSys. 145--158."},{"key":"e_1_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2012.2210256"},{"key":"e_1_2_1_32_1","volume-title":"SSD extension for DiskSim simulation environment. Microsoft Reseach","author":"Prabhakaran Vijayan","year":"2009","unstructured":"Vijayan Prabhakaran and Ted Wobber . 2009. SSD extension for DiskSim simulation environment. Microsoft Reseach ( 2009 ). Vijayan Prabhakaran and Ted Wobber. 2009. SSD extension for DiskSim simulation environment. Microsoft Reseach (2009)."},{"key":"e_1_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1145\/2168836.2168863"},{"key":"e_1_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1109\/SC.2016.47"},{"key":"e_1_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1145\/2038642.2038694"},{"key":"e_1_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1145\/1542275.1542324"},{"key":"e_1_2_1_37_1","doi-asserted-by":"crossref","unstructured":"Rujia Wang Lei Jiang Youtao Zhang and Jun Yang. 2015. SD-PCM: Constructing reliable super dense phase change memory under write disturbance. In ASPOLS. 19--31.  Rujia Wang Lei Jiang Youtao Zhang and Jun Yang. 2015. SD-PCM: Constructing reliable super dense phase change memory under write disturbance. In ASPOLS. 19--31.","DOI":"10.1145\/2775054.2694352"},{"key":"e_1_2_1_38_1","doi-asserted-by":"crossref","unstructured":"Wujie Wen Yaojun Zhang Mengjie Mao and Yiran Chen. 2014. State-restrict MLC STT-RAM designs for high-reliable high-performance memory system. In DAC. 1--6.  Wujie Wen Yaojun Zhang Mengjie Mao and Yiran Chen. 2014. State-restrict MLC STT-RAM designs for high-reliable high-performance memory system. In DAC. 1--6.","DOI":"10.1109\/DAC.2014.6881362"},{"key":"e_1_2_1_39_1","unstructured":"Wikipedia. 2010. Battery or supercap. https:\/\/en.wikipedia.org\/wiki\/Supercapacitor.  Wikipedia. 2010. Battery or supercap. https:\/\/en.wikipedia.org\/wiki\/Supercapacitor."},{"key":"e_1_2_1_40_1","unstructured":"Mai Zheng Joseph Tucek Feng Qin and Mark Lillibridge. 2013. Understanding the robustness of SSDS under power fault. In FAST. 271--284.  Mai Zheng Joseph Tucek Feng Qin and Mark Lillibridge. 2013. Understanding the robustness of SSDS under power fault. In FAST. 271--284."}],"container-title":["ACM Transactions on Design Automation of Electronic Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3131850","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3131850","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T02:13:59Z","timestamp":1750212839000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3131850"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,10,5]]},"references-count":40,"journal-issue":{"issue":"2","published-print":{"date-parts":[[2018,3,31]]}},"alternative-id":["10.1145\/3131850"],"URL":"https:\/\/doi.org\/10.1145\/3131850","relation":{},"ISSN":["1084-4309","1557-7309"],"issn-type":[{"value":"1084-4309","type":"print"},{"value":"1557-7309","type":"electronic"}],"subject":[],"published":{"date-parts":[[2017,10,5]]},"assertion":[{"value":"2007-01-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2009-07-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2017-10-05","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}