{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,21]],"date-time":"2026-01-21T11:24:40Z","timestamp":1768994680720,"version":"3.49.0"},"publisher-location":"New York, NY, USA","reference-count":45,"publisher":"ACM","license":[{"start":{"date-parts":[[2017,10,2]],"date-time":"2017-10-02T00:00:00Z","timestamp":1506902400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"European Union","award":["671578"],"award-info":[{"award-number":["671578"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2017,10,2]]},"DOI":"10.1145\/3132402.3132416","type":"proceedings-article","created":{"date-parts":[[2017,10,12]],"date-time":"2017-10-12T12:51:09Z","timestamp":1507812669000},"page":"283-292","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":14,"title":["Enabling a reliable STT-MRAM main memory simulation"],"prefix":"10.1145","author":[{"given":"Kazi","family":"Asifuzzaman","sequence":"first","affiliation":[{"name":"Universitat Polit\u00e8cnica de Catalunya, Barcelona, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Rommel S\u00e1nchez","family":"Verdejo","sequence":"additional","affiliation":[{"name":"Universitat Polit\u00e8cnica de Catalunya, Barcelona, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Petar","family":"Radojkovi\u0107","sequence":"additional","affiliation":[{"name":"Barcelona Supercomputing Center, Barcelona, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2017,10,2]]},"reference":[{"key":"e_1_3_2_1_1_1","volume-title":"September","author":"Kogge Peter","year":"2008","unstructured":"Peter Kogge , ExaScale Computing Study: Technology Challenges in Achieving Exascale Systems , September 2008 . Peter Kogge, et al. ExaScale Computing Study: Technology Challenges in Achieving Exascale Systems, September 2008."},{"key":"e_1_3_2_1_2_1","volume-title":"Race to Exascale: Opportunities and Challenges. Keynote Presentation at the 44th Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO)","author":"Sodani Avinash","year":"2011","unstructured":"Avinash Sodani . Race to Exascale: Opportunities and Challenges. Keynote Presentation at the 44th Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO) , 2011 . Avinash Sodani. Race to Exascale: Opportunities and Challenges. Keynote Presentation at the 44th Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO), 2011."},{"key":"e_1_3_2_1_3_1","volume-title":"March","author":"Stevens Rick","year":"2010","unstructured":"Rick Stevens , A Decadal DOE Plan for Providing Exascale Applications and Technologies for DOE Mission Needs. Presentation at Advanced Simulation and Computing Principal Investigators Meeting , March 2010 . Rick Stevens, et al. A Decadal DOE Plan for Providing Exascale Applications and Technologies for DOE Mission Needs. Presentation at Advanced Simulation and Computing Principal Investigators Meeting, March 2010."},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.5555\/1855094"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/216585.216588"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/L-CA.2011.4"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/1105734.1105748"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1103\/PhysRevB.43.1297"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/20.486520"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1103\/PhysRevLett.84.3149"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2005.1609379"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2011.20"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1038\/nmat2804"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/LMAG.2016.2539256"},{"key":"e_1_3_2_1_15_1","volume-title":"Novel Hybrid DRAM\/MRAM Design for Reducing Power of High Performance Mobile CPU. In IEEE International Electron Devices Meeting (IEDM)","author":"Abe K.","year":"2012","unstructured":"K. Abe , Novel Hybrid DRAM\/MRAM Design for Reducing Power of High Performance Mobile CPU. In IEEE International Electron Devices Meeting (IEDM) , 2012 . K. Abe, et al. Novel Hybrid DRAM\/MRAM Design for Reducing Power of High Performance Mobile CPU. In IEEE International Electron Devices Meeting (IEDM), 2012."},{"key":"e_1_3_2_1_16_1","volume-title":"Symposium on VLSI Technology (VLSIT)","author":"Noguchi H.","year":"2013","unstructured":"H. Noguchi , A 250-MHz 256b-I\/O 1-Mb STT-MRAM with Advanced Perpendicular MTJ Based Dual cell for Nonvolatile Magnetic Caches to Reduce Active Power of Processors . In Symposium on VLSI Technology (VLSIT) , 2013 . H. Noguchi, et al. A 250-MHz 256b-I\/O 1-Mb STT-MRAM with Advanced Perpendicular MTJ Based Dual cell for Nonvolatile Magnetic Caches to Reduce Active Power of Processors. In Symposium on VLSI Technology (VLSIT), 2013."},{"key":"e_1_3_2_1_17_1","volume-title":"MRAM. In IEEE International Solid-State Circuits Conference","author":"Nebashi R.","year":"2009","unstructured":"R. Nebashi , A 90nm 12ns 32Mb 2T1MTJ MRAM. In IEEE International Solid-State Circuits Conference , 2009 . R. Nebashi, et al. A 90nm 12ns 32Mb 2T1MTJ MRAM. In IEEE International Solid-State Circuits Conference, 2009."},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2017.7870428"},{"key":"e_1_3_2_1_19_1","unstructured":"Everspin Technologies Inc. Everspin displays both the 1Gb DDR4 Perpendicular ST-MRAM device and a 1GByte DDR3 Memory Module (DIMM) at Stand A3-545. https:\/\/www.everspin.com\/news\/everspin-previews-upcoming-products-electronica 2016.  Everspin Technologies Inc. Everspin displays both the 1Gb DDR4 Perpendicular ST-MRAM device and a 1GByte DDR3 Memory Module (DIMM) at Stand A3-545. https:\/\/www.everspin.com\/news\/everspin-previews-upcoming-products-electronica 2016."},{"key":"e_1_3_2_1_20_1","volume-title":"Magneto-resistive memory device including source line voltage generator","author":"Kim H.","year":"2013","unstructured":"H. Kim , Magneto-resistive memory device including source line voltage generator , 2013 . US Patent App . 13\/832,101. H. Kim, et al. Magneto-resistive memory device including source line voltage generator, 2013. US Patent App. 13\/832,101."},{"key":"e_1_3_2_1_21_1","volume-title":"System Including the Same and Method of Reading Data in the Same","author":"Oh H.R.","year":"2014","unstructured":"H.R. Oh . Resistive Memory Device , System Including the Same and Method of Reading Data in the Same , 2014 . US Patent App. 14\/094,021. H.R. Oh. Resistive Memory Device, System Including the Same and Method of Reading Data in the Same, 2014. US Patent App. 14\/094,021."},{"key":"e_1_3_2_1_22_1","volume-title":"Magnetic random access memory","author":"Kim C.","year":"2013","unstructured":"C. Kim , Magnetic random access memory , 2013 . US Patent App . 13\/768,858. C. Kim, et al. Magnetic random access memory, 2013. US Patent App. 13\/768,858."},{"key":"e_1_3_2_1_23_1","unstructured":"Everspin Technologies Inc. Everspin Enhances RIM Smart Meters with Instantly Non-Volatile Low-Energy MRAM Memory. http:\/\/www.everspin.com\/everspin-embedded-mram 2015.  Everspin Technologies Inc. Everspin Enhances RIM Smart Meters with Instantly Non-Volatile Low-Energy MRAM Memory. http:\/\/www.everspin.com\/everspin-embedded-mram 2015."},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1145\/2627369.2627610"},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2012.82"},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2013.6557176"},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1145\/1186736.1186737"},{"key":"e_1_3_2_1_29_1","unstructured":"Top500. Top500 Supercomuter Sites. http:\/\/www.top500.org\/ 2017.  Top500. Top500 Supercomuter Sites. http:\/\/www.top500.org\/ 2017."},{"key":"e_1_3_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1145\/2485922.2485963"},{"key":"e_1_3_2_1_31_1","volume-title":"Intel 64 and IA-32 Architectures Software Developer Manuals","author":"Intel Corporation","year":"2017","unstructured":"Intel Corporation . Intel 64 and IA-32 Architectures Software Developer Manuals , 2017 . Intel Corporation. Intel 64 and IA-32 Architectures Software Developer Manuals, 2017."},{"key":"e_1_3_2_1_32_1","volume-title":"Intel\u00ae 64 and IA-32 Architectures Optimization Reference Manual","year":"2015","unstructured":"Intel. Intel\u00ae 64 and IA-32 Architectures Optimization Reference Manual , 2015 . Intel. Intel\u00ae 64 and IA-32 Architectures Optimization Reference Manual, 2015."},{"key":"e_1_3_2_1_33_1","volume-title":"Reverse Engineering Intel Last-Level Cache Complex Addressing Using Performance Counters","author":"Maurice Cl\u00e9mentine","year":"2015","unstructured":"Cl\u00e9mentine Maurice , Reverse Engineering Intel Last-Level Cache Complex Addressing Using Performance Counters . 2015 . Cl\u00e9mentine Maurice, et al. Reverse Engineering Intel Last-Level Cache Complex Addressing Using Performance Counters. 2015."},{"key":"e_1_3_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1145\/2989081.2989082"},{"key":"e_1_3_2_1_35_1","volume-title":"McVoy and Carl Staelin. Lmbench: Portable Tools for Performance Analysis. In Proceedings of the Annual Conference on USENIX Annual Technical Conference, (ATEC)","author":"Larry","year":"1996","unstructured":"Larry McVoy and Carl Staelin. Lmbench: Portable Tools for Performance Analysis. In Proceedings of the Annual Conference on USENIX Annual Technical Conference, (ATEC) , 1996 . Larry McVoy and Carl Staelin. Lmbench: Portable Tools for Performance Analysis. In Proceedings of the Annual Conference on USENIX Annual Technical Conference, (ATEC), 1996."},{"key":"e_1_3_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2009.4798259"},{"key":"e_1_3_2_1_38_1","volume-title":"Data Intensive Applications. In IEEE International Conference on Cluster Computing (CLUSTER)","author":"Suresh A.","year":"2014","unstructured":"A. Suresh , P. Cicotti , and L. Carrington . Evaluation of Emerging Memory Technologies for HPC , Data Intensive Applications. In IEEE International Conference on Cluster Computing (CLUSTER) , 2014 . A. Suresh, P. Cicotti, and L. Carrington. Evaluation of Emerging Memory Technologies for HPC, Data Intensive Applications. In IEEE International Conference on Cluster Computing (CLUSTER), 2014."},{"key":"e_1_3_2_1_39_1","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2016.7427985"},{"key":"e_1_3_2_1_40_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2012.2185930"},{"key":"e_1_3_2_1_41_1","volume-title":"Yinlong Xu. STT-RAM Based Energy-Efficiency Hybrid Cache for CMPs. In IEEE\/IFIP 19th International Conference on VLSI and System-on-Chip (VLSI-SoC)","author":"Li Jianhua","year":"2011","unstructured":"Jianhua Li , C.J. Xue , and Yinlong Xu. STT-RAM Based Energy-Efficiency Hybrid Cache for CMPs. In IEEE\/IFIP 19th International Conference on VLSI and System-on-Chip (VLSI-SoC) , 2011 . Jianhua Li, C.J. Xue, and Yinlong Xu. STT-RAM Based Energy-Efficiency Hybrid Cache for CMPs. In IEEE\/IFIP 19th International Conference on VLSI and System-on-Chip (VLSI-SoC), 2011."},{"key":"e_1_3_2_1_42_1","doi-asserted-by":"publisher","DOI":"10.1145\/1687399.1687448"},{"key":"e_1_3_2_1_43_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2013.6522314"},{"key":"e_1_3_2_1_44_1","doi-asserted-by":"publisher","DOI":"10.5555\/2014698.2014895"},{"key":"e_1_3_2_1_45_1","doi-asserted-by":"publisher","DOI":"10.1109\/TMAG.2011.2159262"},{"key":"e_1_3_2_1_46_1","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228406"},{"key":"e_1_3_2_1_47_1","doi-asserted-by":"publisher","DOI":"10.1145\/2155620.2155659"}],"event":{"name":"MEMSYS 2017: The International Symposium on Memory Systems, 2017","location":"Alexandria Virginia","acronym":"MEMSYS 2017"},"container-title":["Proceedings of the International Symposium on Memory Systems"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3132402.3132416","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3132402.3132416","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T02:11:15Z","timestamp":1750212675000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3132402.3132416"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,10,2]]},"references-count":45,"alternative-id":["10.1145\/3132402.3132416","10.1145\/3132402"],"URL":"https:\/\/doi.org\/10.1145\/3132402.3132416","relation":{},"subject":[],"published":{"date-parts":[[2017,10,2]]},"assertion":[{"value":"2017-10-02","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}