{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,27]],"date-time":"2025-06-27T04:05:59Z","timestamp":1750997159751,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":3,"publisher":"ACM","license":[{"start":{"date-parts":[[2017,10,2]],"date-time":"2017-10-02T00:00:00Z","timestamp":1506902400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2017,10,2]]},"DOI":"10.1145\/3132402.3132425","type":"proceedings-article","created":{"date-parts":[[2017,10,12]],"date-time":"2017-10-12T12:51:09Z","timestamp":1507812669000},"page":"249-250","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["The interaction of last-level-cache mechanisms on modern processors"],"prefix":"10.1145","author":[{"given":"Rakhi","family":"Hemani","sequence":"first","affiliation":[{"name":"IIIT-Delhi, India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Subhasis","family":"Banerjee","sequence":"additional","affiliation":[{"name":"IBM-Bangalore, India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Apala","family":"Guha","sequence":"additional","affiliation":[{"name":"IIIT-Delhi, India"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2017,10,2]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"crossref","unstructured":"J. Lin Q. Lu X. Ding Z. Zhang X. Zhang and P. Sadayappan. 2008. Gaining insights into multicore cache partitioning: Bridging the gap between simulation and real systems in 14th International Symposium on High Performance Computer Architecture. 367--378 J. Lin Q. Lu X. Ding Z. Zhang X. Zhang and P. Sadayappan. 2008. Gaining insights into multicore cache partitioning: Bridging the gap between simulation and real systems in 14 th International Symposium on High Performance Computer Architecture. 367--378","DOI":"10.1109\/HPCA.2008.4658653"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.49"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/EUC.2014.18"}],"event":{"name":"MEMSYS 2017: The International Symposium on Memory Systems, 2017","acronym":"MEMSYS 2017","location":"Alexandria Virginia"},"container-title":["Proceedings of the International Symposium on Memory Systems"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3132402.3132425","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3132402.3132425","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,26]],"date-time":"2025-06-26T11:24:11Z","timestamp":1750937051000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3132402.3132425"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,10,2]]},"references-count":3,"alternative-id":["10.1145\/3132402.3132425","10.1145\/3132402"],"URL":"https:\/\/doi.org\/10.1145\/3132402.3132425","relation":{},"subject":[],"published":{"date-parts":[[2017,10,2]]},"assertion":[{"value":"2017-10-02","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}