{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T04:34:36Z","timestamp":1750221276587,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":12,"publisher":"ACM","license":[{"start":{"date-parts":[[2017,10,2]],"date-time":"2017-10-02T00:00:00Z","timestamp":1506902400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2017,10,2]]},"DOI":"10.1145\/3132402.3132429","type":"proceedings-article","created":{"date-parts":[[2017,10,12]],"date-time":"2017-10-12T12:51:09Z","timestamp":1507812669000},"page":"177-179","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["Logging in persistent memory"],"prefix":"10.1145","author":[{"given":"Mengjie","family":"Li","sequence":"first","affiliation":[{"name":"University of California"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Matheus","family":"Ogleari","sequence":"additional","affiliation":[{"name":"University of California"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jishen","family":"Zhao","sequence":"additional","affiliation":[{"name":"University of California"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2017,10,2]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"Intel write combining memory implementation guidelines. http:\/\/download.intel.com\/design\/PentiumII\/applnots\/24442201.pdf.  Intel write combining memory implementation guidelines. http:\/\/download.intel.com\/design\/PentiumII\/applnots\/24442201.pdf."},{"key":"e_1_3_2_1_2_1","unstructured":"Perf wiki. http:\/\/perf.wiki.kernel.org\/.  Perf wiki. http:\/\/perf.wiki.kernel.org\/."},{"key":"e_1_3_2_1_3_1","volume-title":"Proceedings of the Memory Workshop","author":"Cagli C.","year":"2012","unstructured":"C. Cagli . Characterization and modelling of electrode impact in HfO2-based RRAM . In Proceedings of the Memory Workshop , 2012 . C. Cagli. Characterization and modelling of electrode impact in HfO2-based RRAM. In Proceedings of the Memory Workshop, 2012."},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/1950365.1950380"},{"volume-title":"Intel architecture instruction set extensions programming reference","year":"2016","key":"e_1_3_2_1_5_1","unstructured":"Intel. Intel architecture instruction set extensions programming reference , 2016 . https:\/\/software.intel.com\/sites\/default\/files\/managed\/c5\/15\/architecture-instruction-set-extensions-programming-reference.pdf. Intel. Intel architecture instruction set extensions programming reference, 2016. https:\/\/software.intel.com\/sites\/default\/files\/managed\/c5\/15\/architecture-instruction-set-extensions-programming-reference.pdf."},{"key":"e_1_3_2_1_6_1","volume-title":"Intel and Micron produce breakthrough memory technology","author":"Micron Intel","year":"2015","unstructured":"Intel and Micron . Intel and Micron produce breakthrough memory technology , 2015 . http:\/\/newsroom.intel.com\/community\/intel_newsroom\/. Intel and Micron. Intel and Micron produce breakthrough memory technology, 2015. http:\/\/newsroom.intel.com\/community\/intel_newsroom\/."},{"key":"e_1_3_2_1_7_1","volume-title":"Intel White Paper","author":"Paoloni G.","year":"2010","unstructured":"G. Paoloni . Intel , how to benchmark code execution times on Intel IA-32 and IA-64 instruction set architectures . In Intel White Paper , 2010 . G. Paoloni. Intel, how to benchmark code execution times on Intel IA-32 and IA-64 instruction set architectures. In Intel White Paper, 2010."},{"key":"e_1_3_2_1_8_1","volume-title":"Proceedings of the Memory Workshop","author":"Sousa V.","year":"2012","unstructured":"V. Sousa . Phase change materials engineering for RESET current reduction . In Proceedings of the Memory Workshop , 2012 . V. Sousa. Phase change materials engineering for RESET current reduction. In Proceedings of the Memory Workshop, 2012."},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/1950365.1950379"},{"key":"e_1_3_2_1_10_1","first-page":"323","volume-title":"14th USENIX Conference on File and Storage Technologies (FAST 16)","author":"Xu J.","year":"2016","unstructured":"J. Xu and S. Swanson . NOVA: A log-structured file system for hybrid volatile\/non-volatile main memories . In 14th USENIX Conference on File and Storage Technologies (FAST 16) , pages 323 -- 338 , 2016 . J. Xu and S. Swanson. NOVA: A log-structured file system for hybrid volatile\/non-volatile main memories. In 14th USENIX Conference on File and Storage Technologies (FAST 16), pages 323--338, 2016."},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2014.47"},{"key":"e_1_3_2_1_12_1","first-page":"40","volume-title":"Behavioral Modeling and Simulation Workshop","author":"Zhao W.","year":"2006","unstructured":"W. Zhao , E. Belhaire , and Q. Mistral et al. Macro-model of spin-transfer torque based magnetic tunnel junction device for hybrid magnetic-CMOS design . In Behavioral Modeling and Simulation Workshop , pages 40 -- 43 , 2006 . W. Zhao, E. Belhaire, and Q. Mistral et al. Macro-model of spin-transfer torque based magnetic tunnel junction device for hybrid magnetic-CMOS design. In Behavioral Modeling and Simulation Workshop, pages 40--43, 2006."}],"event":{"name":"MEMSYS 2017: The International Symposium on Memory Systems, 2017","acronym":"MEMSYS 2017","location":"Alexandria Virginia"},"container-title":["Proceedings of the International Symposium on Memory Systems"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3132402.3132429","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3132402.3132429","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T02:11:15Z","timestamp":1750212675000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3132402.3132429"}},"subtitle":["to cache, or not to cache?"],"short-title":[],"issued":{"date-parts":[[2017,10,2]]},"references-count":12,"alternative-id":["10.1145\/3132402.3132429","10.1145\/3132402"],"URL":"https:\/\/doi.org\/10.1145\/3132402.3132429","relation":{},"subject":[],"published":{"date-parts":[[2017,10,2]]},"assertion":[{"value":"2017-10-02","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}