{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:49:38Z","timestamp":1750308578736,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":28,"publisher":"ACM","license":[{"start":{"date-parts":[[2017,10,2]],"date-time":"2017-10-02T00:00:00Z","timestamp":1506902400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by-nc-nd\/4.0\/"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2017,10,2]]},"DOI":"10.1145\/3132402.3132430","type":"proceedings-article","created":{"date-parts":[[2017,10,12]],"date-time":"2017-10-12T12:51:09Z","timestamp":1507812669000},"page":"15-25","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":1,"title":["PHOENIX"],"prefix":"10.1145","author":[{"given":"Mats","family":"Rimborg","sequence":"first","affiliation":[{"name":"Chalmers University of Technology, Gothenburg, Sweden"}]},{"given":"Pedro","family":"Trancoso","sequence":"additional","affiliation":[{"name":"Chalmers University of Technology, Gothenburg, Sweden and University of Cyprus, Nicosia, Cyprus"}]},{"given":"Gunnar","family":"Carlstedt","sequence":"additional","affiliation":[{"name":"Chalmers University of Technology, Gothenburg, Sweden"}]}],"member":"320","published-online":{"date-parts":[[2017,10,2]]},"reference":[{"doi-asserted-by":"publisher","key":"e_1_3_2_1_1_1","DOI":"10.1109\/MM.2016.25"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_2_1","DOI":"10.1147\/rd.515.0559"},{"key":"e_1_3_2_1_3_1","first-page":"01832","article-title":"Epiphany-V: A 1024 processor 64-bit RISC system-on-chip","volume":"1610","author":"Olofsson A.","year":"2016","unstructured":"A. Olofsson , \" Epiphany-V: A 1024 processor 64-bit RISC system-on-chip ,\" CoRR , vol. abs\/ 1610 . 01832 , 2016 . {Online}. Available: http:\/\/arxiv.org\/abs\/1610.01832 A. Olofsson, \"Epiphany-V: A 1024 processor 64-bit RISC system-on-chip,\" CoRR, vol. abs\/1610.01832, 2016. {Online}. Available: http:\/\/arxiv.org\/abs\/1610.01832","journal-title":"CoRR"},{"unstructured":"A. Olofsson \"How to build a Megacore microprocessor \" HiPEAC17 2017. {Online}. Available: https:\/\/www.parallella.org\/wp-content\/uploads\/2017\/01\/million_cores.pdf  A. Olofsson \"How to build a Megacore microprocessor \" HiPEAC17 2017. {Online}. Available: https:\/\/www.parallella.org\/wp-content\/uploads\/2017\/01\/million_cores.pdf","key":"e_1_3_2_1_4_1"},{"key":"e_1_3_2_1_5_1","first-page":"1","article-title":"Nvidia tesla p100","volume":"01","author":"NVIDIA","year":"2016","unstructured":"NVIDIA , \" Nvidia tesla p100 ,\" NVIDIA Corporation, Tech. Rep. WP-08019--001 v 01 . 1 , 2016 . NVIDIA, \"Nvidia tesla p100,\" NVIDIA Corporation, Tech. Rep. WP-08019--001 v01.1, 2016.","journal-title":"NVIDIA Corporation, Tech. Rep. WP-08019--001"},{"key":"e_1_3_2_1_7_1","volume-title":"A processing in memory taxonomy and a case for studying fixed-function PIM,\" 46th IEEE\/ACM International Symposium on microarchitecture (micro-46)","author":"G. Loh","year":"2013","unstructured":"G. Loh et al , \" A processing in memory taxonomy and a case for studying fixed-function PIM,\" 46th IEEE\/ACM International Symposium on microarchitecture (micro-46) , 2013 . G. Loh et al, \"A processing in memory taxonomy and a case for studying fixed-function PIM,\" 46th IEEE\/ACM International Symposium on microarchitecture (micro-46), 2013."},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_8_1","DOI":"10.1109\/ICCD.2012.6378607"},{"key":"e_1_3_2_1_9_1","volume-title":"Micron's Yukon,\" Proceedings International Parallel and Distributed Processing Symposium (IPDPS)","author":"Kirsch G.","year":"2003","unstructured":"G. Kirsch , \" Active memory : Micron's Yukon,\" Proceedings International Parallel and Distributed Processing Symposium (IPDPS) , 2003 . G. Kirsch, \"Active memory: Micron's Yukon,\" Proceedings International Parallel and Distributed Processing Symposium (IPDPS), 2003."},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_10_1","DOI":"10.1109\/TPDS.2014.8"},{"key":"e_1_3_2_1_11_1","volume-title":"Inc.","author":"Pawlowski J. T.","year":"2011","unstructured":"J. T. Pawlowski , \" Hybrid memory cube (HMC) : Breakthrough DRAM performance with a fundamentally re-architected DRAM subsystem,\" in Hot Chips 23. Boise, ID, USA: Micron Technology , Inc. , 2011 . {Online}. Available : http:\/\/hotchips.org\/wp-content\/uploads\/hc_archives\/hc23\/HC23.18.3-memory-FPGA\/HC23.18.320-HybridCube-Pawlowski-Micron.pdf J. T. Pawlowski, \"Hybrid memory cube (HMC): Breakthrough DRAM performance with a fundamentally re-architected DRAM subsystem,\" in Hot Chips 23. Boise, ID, USA: Micron Technology, Inc., 2011. {Online}. Available: http:\/\/hotchips.org\/wp-content\/uploads\/hc_archives\/hc23\/HC23.18.3-memory-FPGA\/HC23.18.320-HybridCube-Pawlowski-Micron.pdf"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_12_1","DOI":"10.1147\/JRD.2015.2409732"},{"key":"e_1_3_2_1_13_1","first-page":"489","volume-title":"IPDPS Workshops","author":"Aguilera Paula","year":"2016","unstructured":"Paula Aguilera , Dong Ping Zhang , Nam Sung Kim , Nuwan Jayasena , \" Fine-Grained Task Migration for Graph Algorithms Using Processing in Memory ,\" IPDPS Workshops 2016 , pp 489 -- 498 Paula Aguilera, Dong Ping Zhang, Nam Sung Kim, Nuwan Jayasena, \"Fine-Grained Task Migration for Graph Algorithms Using Processing in Memory,\" IPDPS Workshops 2016, pp 489--498"},{"volume-title":"Dong Ping Zhang","author":"Breslow Alex D.","unstructured":"Alex D. Breslow , Dong Ping Zhang , Joseph L. Greathouse , Nuwan Jayasena , Dean M. Tullsen: Horton Tables, \"Fast Hash Tables for InMemory Data-Intensive Computing,\" USENIX Annual Technical Conference 2016, pp 281--294 Alex D. Breslow, Dong Ping Zhang, Joseph L. Greathouse, Nuwan Jayasena, Dean M. Tullsen: Horton Tables, \"Fast Hash Tables for InMemory Data-Intensive Computing,\" USENIX Annual Technical Conference 2016, pp 281--294","key":"e_1_3_2_1_14_1"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_15_1","DOI":"10.1145\/2600212.2600213"},{"key":"e_1_3_2_1_16_1","first-page":"1","article-title":"A new perspective on processing-in-memory architecture design","author":"Zhang Dong Ping","year":"2013","unstructured":"Dong Ping Zhang , Nuwan Jayasena , Alexander Lyashevsky , Joseph L. Greathouse , Mitesh R. Meswani , Mark Nutter , Mike Ignatowski , \" A new perspective on processing-in-memory architecture design ,\" MSPC@PLDI 2013 , pp 7: 1 -- 7 :3 Dong Ping Zhang, Nuwan Jayasena, Alexander Lyashevsky, Joseph L. Greathouse, Mitesh R. Meswani, Mark Nutter, Mike Ignatowski, \"A new perspective on processing-in-memory architecture design,\" MSPC@PLDI 2013, pp 7:1--7:3","journal-title":"MSPC@PLDI"},{"key":"e_1_3_2_1_17_1","first-page":"43","article-title":"Processing-in-Memory: Exploring the Design Space","author":"Scrbak Marko","year":"2015","unstructured":"Marko Scrbak , Mahzabeen Islam , Krishna M. Kavi , Mike Ignatowski , Nuwan Jayasena , \" Processing-in-Memory: Exploring the Design Space ,\" ARCS 2015 , pp 43 -- 54 Marko Scrbak, Mahzabeen Islam, Krishna M. Kavi, Mike Ignatowski, Nuwan Jayasena, \"Processing-in-Memory: Exploring the Design Space,\" ARCS 2015, pp 43--54","journal-title":"ARCS"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_18_1","DOI":"10.1145\/2749469.2750386"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_19_1","DOI":"10.1007\/s11265-014-0896-x"},{"key":"e_1_3_2_1_20_1","first-page":"3.7.1","volume-title":"Dec 2014","author":"S. Natarajan","unstructured":"S. Natarajan et al., \" A 14nm logic technology featuring 2nd generation finfet, air-gapped interconnects, self-aligned double patterning and a 0.0588μm2 sram cell size,\" in 2014 IEEE International Electron Devices Meeting , Dec 2014 , pp. 3.7.1 -- 3.7.3 . S. Natarajan et al., \"A 14nm logic technology featuring 2nd generation finfet, air-gapped interconnects, self-aligned double patterning and a 0.0588μm2 sram cell size,\" in 2014 IEEE International Electron Devices Meeting, Dec 2014, pp. 3.7.1--3.7.3."},{"key":"e_1_3_2_1_21_1","first-page":"3.3.1","volume-title":"2012 International Electron Devices Meeting","author":"S. Narasimha","year":"2012","unstructured":"S. Narasimha et al., \"22nm High-Performance SOI Technology Featuring Dual-Embedded Stressors, Epi-Plate High-K Deep-Trench Embedded DRAM and Self-Aligned Via 15LM BEOL,\" in 2012 International Electron Devices Meeting , Dec 2012 , pp. 3.3.1 -- 3.3.4 . S. Narasimha et al., \"22nm High-Performance SOI Technology Featuring Dual-Embedded Stressors, Epi-Plate High-K Deep-Trench Embedded DRAM and Self-Aligned Via 15LM BEOL,\" in 2012 International Electron Devices Meeting, Dec 2012, pp. 3.3.1--3.3.4."},{"key":"e_1_3_2_1_22_1","first-page":"1","volume-title":"Low-k iterconnect stack with metal-insulatormetal capacitors for 22nm high","author":"D. Ingerly","year":"2012","unstructured":"D. Ingerly et al. , \" Low-k iterconnect stack with metal-insulatormetal capacitors for 22nm high volume manufacturing,\" in 2012 IEEE International Interconnect Technology Conference , June 2012 , pp. 1 -- 3 . D. Ingerly et al., \"Low-k iterconnect stack with metal-insulatormetal capacitors for 22nm high volume manufacturing,\" in 2012 IEEE International Interconnect Technology Conference, June 2012, pp. 1--3."},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_23_1","DOI":"10.1109\/IEDM.2014.7046977"},{"key":"e_1_3_2_1_24_1","first-page":"33","volume-title":"C.-M","author":"Lee J.-H.","year":"2016","unstructured":"J.-H. Lee , \" Bulk finfets : Design at 14 nm node and key characteristics,\" in Nano Devices and Circuit Techniques for Low-Energy Applications and Energy Harvesting , C.-M . Kyung, Ed. Dordrecht : Springer Netherlands , 2016 , pp. 33 -- 64 . J.-H. Lee, \"Bulk finfets: Design at 14 nm node and key characteristics,\" in Nano Devices and Circuit Techniques for Low-Energy Applications and Energy Harvesting, C.-M. Kyung, Ed. Dordrecht: Springer Netherlands, 2016, pp. 33--64."},{"key":"e_1_3_2_1_25_1","first-page":"96","volume-title":"Feb 2014","author":"Fluhr E. J.","unstructured":"E. J. Fluhr : A 12-core Server-Class Processor in 22nm SOI with 7.6Tb\/s Off-Chip Bandwidth,\" in 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC) , Feb 2014 , pp. 96 -- 97 . E. J. Fluhr et al., \"5.1 POWER8\u2122: A 12-core Server-Class Processor in 22nm SOI with 7.6Tb\/s Off-Chip Bandwidth,\" in 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), Feb 2014, pp. 96--97."},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_26_1","DOI":"10.1109\/JSSC.2015.2456873"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_27_1","DOI":"10.1090\/S0025-5718-1965-0178586-1"},{"key":"e_1_3_2_1_28_1","first-page":"796","article-title":"Improving latency in a signal processing system on the epiphany architecture","volume":"2016","author":"Brauer P.","year":"2016","unstructured":"P. Brauer , M. Lundqvist , and A. M\u00e4llo , \" Improving latency in a signal processing system on the epiphany architecture ,\" in Proceedings of PDP 2016 , Feb 2016 , pp. 796 -- 800 . P. Brauer, M. Lundqvist, and A. M\u00e4llo, \"Improving latency in a signal processing system on the epiphany architecture,\" in Proceedings of PDP 2016, Feb 2016, pp. 796--800.","journal-title":"Proceedings of PDP"},{"unstructured":"S. Hall \"FFT Optimizations for GPU and Many-Core Architectures \" AUT University Tech. Rep. 2016.  S. Hall \"FFT Optimizations for GPU and Many-Core Architectures \" AUT University Tech. Rep. 2016.","key":"e_1_3_2_1_29_1"}],"event":{"acronym":"MEMSYS 2017","name":"MEMSYS 2017: The International Symposium on Memory Systems, 2017","location":"Alexandria Virginia"},"container-title":["Proceedings of the International Symposium on Memory Systems"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3132402.3132430","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3132402.3132430","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T19:04:56Z","timestamp":1750273496000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3132402.3132430"}},"subtitle":["efficient computation in memory"],"short-title":[],"issued":{"date-parts":[[2017,10,2]]},"references-count":28,"alternative-id":["10.1145\/3132402.3132430","10.1145\/3132402"],"URL":"https:\/\/doi.org\/10.1145\/3132402.3132430","relation":{},"subject":[],"published":{"date-parts":[[2017,10,2]]},"assertion":[{"value":"2017-10-02","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}