{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T04:35:15Z","timestamp":1750221315827,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":30,"publisher":"ACM","license":[{"start":{"date-parts":[[2017,11,6]],"date-time":"2017-11-06T00:00:00Z","timestamp":1509926400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/501100001459","name":"Ministry of Education - Singapore","doi-asserted-by":"publisher","award":["T1 251RES1610"],"award-info":[{"award-number":["T1 251RES1610"]}],"id":[{"id":"10.13039\/501100001459","id-type":"DOI","asserted-by":"publisher"}]},{"name":"Ministry of Education, Singapore","award":["MOE2017-T2-1-122"],"award-info":[{"award-number":["MOE2017-T2-1-122"]}]},{"DOI":"10.13039\/501100001381","name":"National Research Foundation Singapore","doi-asserted-by":"publisher","award":["IDM Futures Funding Initiative"],"award-info":[{"award-number":["IDM Futures Funding Initiative"]}],"id":[{"id":"10.13039\/501100001381","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2017,11,6]]},"DOI":"10.1145\/3132847.3132916","type":"proceedings-article","created":{"date-parts":[[2017,11,6]],"date-time":"2017-11-06T13:30:29Z","timestamp":1509975029000},"page":"657-666","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":16,"title":["A Study of Main-Memory Hash Joins on Many-core Processor"],"prefix":"10.1145","author":[{"given":"Xuntao","family":"Cheng","sequence":"first","affiliation":[{"name":"Nanyang Technological University, Singapore, Singapore"}]},{"given":"Bingsheng","family":"He","sequence":"additional","affiliation":[{"name":"National University of Singapore, Singapore, Singapore"}]},{"given":"Xiaoli","family":"Du","sequence":"additional","affiliation":[{"name":"National University of Defense Technology, Changsha, China"}]},{"given":"Chiew Tong","family":"Lau","sequence":"additional","affiliation":[{"name":"Nanyang Technological University, Singapore, Singapore"}]}],"member":"320","published-online":{"date-parts":[[2017,11,6]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.14778\/2336664.2336678"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.14778\/2732219.2732227"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/1989323.1989328"},{"key":"e_1_3_2_1_4_1","volume-title":"Kersten","author":"Boncz Peter A.","year":"1999","unstructured":"Peter A. Boncz , Stefan Manegold , and Martin L . Kersten . 1999 . Database Architecture Optimized for the New Bottleneck : Memory Access Proceedings of the 25th International Conference on Very Large Data Bases. Morgan Kaufmann Publishers Inc ., 54--65. Peter A. Boncz, Stefan Manegold, and Martin L. Kersten. 1999. Database Architecture Optimized for the New Bottleneck: Memory Access Proceedings of the 25th International Conference on Very Large Data Bases. Morgan Kaufmann Publishers Inc., 54--65."},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/1272743.1272747"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/2771937.2771939"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/2882903.2899407"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/1376616.1376670"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.14778\/2536206.2536216"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/2751205.2751247"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"crossref","unstructured":"James Jeffers and etal. 2016. Intel Xeon Phi Processor High Performance Programming: Knights Landing Edition. Morgan Kaufmann.   James Jeffers and et al.. 2016. Intel Xeon Phi Processor High Performance Programming: Knights Landing Edition. Morgan Kaufmann.","DOI":"10.1016\/B978-0-12-809194-4.00002-8"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.14778\/2735703.2735704"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/2236584.2236592"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICDE.2011.5767867"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/2588555.2594524"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.14778\/1687553.1687564"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/2882903.2882952"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/2588555.2610507"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/2463676.2465322"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.15"},{"key":"e_1_3_2_1_21_1","first-page":"114","volume-title":"Reprinted from Electronics","author":"Moore G. E.","year":"1965","unstructured":"G. E. Moore . 2006. Cramming more components onto integrated circuits , Reprinted from Electronics , volume 38 , number 8, April 19, 1965 , pp. 114 ff. IEEE Solid-State Circuits Society Newsletter , Vol . 11, 5 (2006), 33--35. G. E. Moore. 2006. Cramming more components onto integrated circuits, Reprinted from Electronics, volume 38, number 8, April 19, 1965, pp.114 ff. IEEE Solid-State Circuits Society Newsletter, Vol. 11, 5 (2006), 33--35."},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.14778\/3007328.3007336"},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1145\/2723372.2747645"},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.14778\/3015274.3015275"},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1145\/1807167.1807207"},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1145\/2882903.2882917"},{"volume-title":"Knights landing (KNL): 2nd Generation Intel\u00ae Xeon Phi processor Hot Chips","author":"Sodani Avinash","key":"e_1_3_2_1_27_1","unstructured":"Avinash Sodani . 2015. Knights landing (KNL): 2nd Generation Intel\u00ae Xeon Phi processor Hot Chips . IEEE , 1--24. Avinash Sodani. 2015. Knights landing (KNL): 2nd Generation Intel\u00ae Xeon Phi processor Hot Chips. IEEE, 1--24."},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1145\/2814710.2814717"},{"key":"e_1_3_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICDE.2013.6544839"},{"key":"e_1_3_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1109\/TKDE.2015.2427795"}],"event":{"name":"CIKM '17: ACM Conference on Information and Knowledge Management","sponsor":["SIGWEB ACM Special Interest Group on Hypertext, Hypermedia, and Web","SIGIR ACM Special Interest Group on Information Retrieval"],"location":"Singapore Singapore","acronym":"CIKM '17"},"container-title":["Proceedings of the 2017 ACM on Conference on Information and Knowledge Management"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3132847.3132916","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3132847.3132916","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T02:13:45Z","timestamp":1750212825000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3132847.3132916"}},"subtitle":["A Case with Intel Knights Landing Architecture"],"short-title":[],"issued":{"date-parts":[[2017,11,6]]},"references-count":30,"alternative-id":["10.1145\/3132847.3132916","10.1145\/3132847"],"URL":"https:\/\/doi.org\/10.1145\/3132847.3132916","relation":{},"subject":[],"published":{"date-parts":[[2017,11,6]]},"assertion":[{"value":"2017-11-06","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}