{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,9,26]],"date-time":"2026-09-26T11:00:01Z","timestamp":1790420401077,"version":"4.1.0"},"publisher-location":"New York, NY, USA","reference-count":41,"publisher":"ACM","license":[{"start":{"date-parts":[[2017,10,4]],"date-time":"2017-10-04T00:00:00Z","timestamp":1507075200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/100000183","name":"Army Research Office","doi-asserted-by":"publisher","award":["W911NF-14-1-0499"],"award-info":[{"award-number":["W911NF-14-1-0499"]}],"id":[{"id":"10.13039\/100000183","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000181","name":"Air Force Office of Scientific Research","doi-asserted-by":"publisher","award":["FA9550-14-1-0161"],"award-info":[{"award-number":["FA9550-14-1-0161"]}],"id":[{"id":"10.13039\/100000181","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000144","name":"Division of Computer and Network Systems","doi-asserted-by":"publisher","award":["1409175, 1563845"],"award-info":[{"award-number":["1409175, 1563845"]}],"id":[{"id":"10.13039\/100000144","id-type":"DOI","asserted-by":"publisher"}]},{"name":"Cyber Physical Systems","award":["1446631"],"award-info":[{"award-number":["1446631"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2017,10,4]]},"DOI":"10.1145\/3139258.3139268","type":"proceedings-article","created":{"date-parts":[[2017,11,8]],"date-time":"2017-11-08T13:20:39Z","timestamp":1510147239000},"page":"58-67","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":12,"title":["Supporting mode changes while providing hardware isolation in mixed-criticality multicore systems"],"prefix":"10.1145","author":[{"given":"Micaiah","family":"Chisholm","sequence":"first","affiliation":[{"name":"University of North Carolina at Chapel Hill"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Namhoon","family":"Kim","sequence":"additional","affiliation":[{"name":"University of North Carolina at Chapel Hill"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Stephen","family":"Tang","sequence":"additional","affiliation":[{"name":"University of North Carolina at Chapel Hill"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Nathan","family":"Otterness","sequence":"additional","affiliation":[{"name":"University of North Carolina at Chapel Hill"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"James H.","family":"Anderson","sequence":"additional","affiliation":[{"name":"University of North Carolina at Chapel Hill"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"F. Donelson","family":"Smith","sequence":"additional","affiliation":[{"name":"University of North Carolina at Chapel Hill"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Donald E.","family":"Porter","sequence":"additional","affiliation":[{"name":"University of North Carolina at Chapel Hill"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2017,10,4]]},"reference":[{"key":"e_1_3_2_1_1_1","volume-title":"RTAS '16","author":"Alhammad A.","unstructured":"A. Alhammad and R. Pellizzoni . Trading cores for memory bandwidth in real-time systems . In RTAS '16 . A. Alhammad and R. Pellizzoni. Trading cores for memory bandwidth in real-time systems. In RTAS '16."},{"key":"e_1_3_2_1_2_1","volume-title":"RTAS '15","author":"Alhammad A","unstructured":"A Alhammad , S. Wasly , and R. Pellizzoni . Memory efficient global scheduling of real-time tasks . In RTAS '15 . A Alhammad, S. Wasly, and R. Pellizzoni. Memory efficient global scheduling of real-time tasks. In RTAS '15."},{"key":"e_1_3_2_1_3_1","volume-title":"ECRTS '14","author":"Altmeyer S.","unstructured":"S. Altmeyer , R. Douma , W. Lunniss , and R. Davis . Evaluation of cache partitioning for hard real-time systems . In ECRTS '14 . S. Altmeyer, R. Douma, W. Lunniss, and R. Davis. Evaluation of cache partitioning for hard real-time systems. In ECRTS '14."},{"key":"e_1_3_2_1_4_1","volume-title":"WMC '13","author":"Audsley N.","unstructured":"N. Audsley . Memory architecture for NoC-based real-time mixed criticality systems . In WMC '13 . N. Audsley. Memory architecture for NoC-based real-time mixed criticality systems. In WMC '13."},{"key":"e_1_3_2_1_5_1","volume-title":"ECRTS '17","author":"Awan M. A.","unstructured":"M. A. Awan , K. Bletsas , P.F. Souto , B. Akesson , and E. Tovar . Mixed-criticality scheduling with dynamic redistribution of shared cache . In ECRTS '17 . M. A. Awan, K. Bletsas, P.F. Souto, B. Akesson, and E. Tovar. Mixed-criticality scheduling with dynamic redistribution of shared cache. In ECRTS '17."},{"key":"e_1_3_2_1_6_1","volume-title":"WMC '14","author":"Burns A.","unstructured":"A. Burns . System mode changes - general and criticality-based . In WMC '14 . A. Burns. System mode changes - general and criticality-based. In WMC '14."},{"key":"e_1_3_2_1_7_1","volume-title":"Department of Computer Science","author":"Burns A.","year":"2014","unstructured":"A. Burns and R. Davis . Mixed criticality systems - a review. Technical report , Department of Computer Science , University of York , 2014 . A. Burns and R. Davis. Mixed criticality systems - a review. Technical report, Department of Computer Science, University of York, 2014."},{"key":"e_1_3_2_1_8_1","volume-title":"May","author":"Software Certification Authorities","year":"2014","unstructured":"Certification Authorities Software Team (CAST). Position paper CAST-32: Multicore processors , May 2014 . Certification Authorities Software Team (CAST). Position paper CAST-32: Multicore processors, May 2014."},{"key":"e_1_3_2_1_9_1","volume-title":"Nov.","author":"Software Certification Authorities","year":"2016","unstructured":"Certification Authorities Software Team (CAST). Position paper CAST-32A: Multi-core processors , Nov. 2016 . Certification Authorities Software Team (CAST). Position paper CAST-32A: Multi-core processors, Nov. 2016."},{"key":"e_1_3_2_1_10_1","volume-title":"RTSS '16","author":"Chisholm M.","unstructured":"M. Chisholm , N. Kim , B. Ward , N. Otterness , J. Anderson , and F.D. Smith . Reconciling the tension between hardware isolation and data sharing in mixed-criticality, multicore systems . In RTSS '16 . M. Chisholm, N. Kim, B. Ward, N. Otterness, J. Anderson, and F.D. Smith. Reconciling the tension between hardware isolation and data sharing in mixed-criticality, multicore systems. In RTSS '16."},{"key":"e_1_3_2_1_11_1","volume-title":"Supporting mode changes while providing hardware isolation in mixed-criticality multicore systems. Full version of this paper,","author":"Chisholm M.","year":"2017","unstructured":"M. Chisholm , S. Tang , N. Kim , N. Otterness , J. Anderson , D. Porter , and F.D. Smith . Supporting mode changes while providing hardware isolation in mixed-criticality multicore systems. Full version of this paper, available at http:\/\/jamesanderson.web.unc.edu\/papers\/, 2017 . M. Chisholm, S. Tang, N. Kim, N. Otterness, J. Anderson, D. Porter, and F.D. Smith. Supporting mode changes while providing hardware isolation in mixed-criticality multicore systems. Full version of this paper, available at http:\/\/jamesanderson.web.unc.edu\/papers\/, 2017."},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/RTSS.2015.36"},{"key":"e_1_3_2_1_13_1","volume-title":"EMSOFT '13","author":"Giannopoulou G.","unstructured":"G. Giannopoulou , N. Stoimenov , P. Huang , and L. Thiele . Scheduling of mixed-criticality applications on resource-sharing multicore systems . In EMSOFT '13 . G. Giannopoulou, N. Stoimenov, P. Huang, and L. Thiele. Scheduling of mixed-criticality applications on resource-sharing multicore systems. In EMSOFT '13."},{"key":"e_1_3_2_1_14_1","volume-title":"RTAS '17","author":"Guo D.","unstructured":"D. Guo and R. Pellizzoni . A requests bundling DRAM controller for mixed-criticality systems . In RTAS '17 . D. Guo and R. Pellizzoni. A requests bundling DRAM controller for mixed-criticality systems. In RTAS '17."},{"key":"e_1_3_2_1_15_1","volume-title":"RTAS '16","author":"Hassan M.","unstructured":"M. Hassan and H. Patel . Criticality- and requirement-aware bus arbitration for multi-core mixed criticality systems . In RTAS '16 . M. Hassan and H. Patel. Criticality- and requirement-aware bus arbitration for multi-core mixed criticality systems. In RTAS '16."},{"key":"e_1_3_2_1_16_1","volume-title":"RTAS '15","author":"Hassan M.","unstructured":"M. Hassan , H. Patel , and R. Pellizzoni . A framework for scheduling DRAM memory accesses for multi-core mixed-time critical systems . In RTAS '15 . M. Hassan, H. Patel, and R. Pellizzoni. A framework for scheduling DRAM memory accesses for multi-core mixed-time critical systems. In RTAS '15."},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/RTAS.2012.24"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/ECRTS.2011.11"},{"key":"e_1_3_2_1_19_1","volume-title":"RTSS '14","author":"Jalle J.","unstructured":"J. Jalle , E. Quinones , J. Abella , L. Fossati , M. Zulianello , and P. Cazorla . A dual-criticality memory controller (DCmc) proposal and evaluation of a space case study . In RTSS '14 . J. Jalle, E. Quinones, J. Abella, L. Fossati, M. Zulianello, and P. Cazorla. A dual-criticality memory controller (DCmc) proposal and evaluation of a space case study. In RTSS '14."},{"key":"e_1_3_2_1_20_1","volume-title":"RTAS '15","author":"Kim H.","unstructured":"H. Kim , D. Broman , E. Lee , M. Zimmer , A. Shrivastava , and J. Oh . A predictable and command-level priority-based DRAM controller for mixed-criticality systems . In RTAS '15 . H. Kim, D. Broman, E. Lee, M. Zimmer, A. Shrivastava, and J. Oh. A predictable and command-level priority-based DRAM controller for mixed-criticality systems. In RTAS '15."},{"key":"e_1_3_2_1_21_1","volume-title":"RTAS '14","author":"Kim H.","unstructured":"H. Kim , D. de Niz , B. Andersson , M. Klein , O. Mutlu , and R. Rajkumar . Bounding memory interference delay in COTS-based multi-core systems . In RTAS '14 . H. Kim, D. de Niz, B. Andersson, M. Klein, O. Mutlu, and R. Rajkumar. Bounding memory interference delay in COTS-based multi-core systems. In RTAS '14."},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1109\/ECRTS.2013.19"},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.sysarc.2013.07.002"},{"key":"e_1_3_2_1_24_1","volume-title":"RTAS '17","author":"Kim N.","unstructured":"N. Kim , M. Chisholm , N. Otterness , J. Anderson , and F.D. Smith . Allowing shared libraries while supporting hardware isolation in multicore real-time systems . In RTAS '17 . N. Kim, M. Chisholm, N. Otterness, J. Anderson, and F.D. Smith. Allowing shared libraries while supporting hardware isolation in multicore real-time systems. In RTAS '17."},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1007\/s11241-017-9272-9"},{"key":"e_1_3_2_1_26_1","volume-title":"RTAS '16","author":"Kim N.","unstructured":"N. Kim , B. Ward , M. Chisholm , C.-Y. Fu , J. Anderson , and F.D. Smith . Attacking the one-out-of-m multicore problem by combining hardware management with mixed-criticality provisioning . In RTAS '16 . N. Kim, B. Ward, M. Chisholm, C.-Y. Fu, J. Anderson, and F.D. Smith. Attacking the one-out-of-m multicore problem by combining hardware management with mixed-criticality provisioning. In RTAS '16."},{"key":"e_1_3_2_1_27_1","volume-title":"WICERT '13","author":"Kotaba O.","unstructured":"O. Kotaba , J. Nowotsch , M. Paulitsch , S. Petters , and H. Theiling . Multicore in real-time systems - temporal isolation challenges due to shared resources . In WICERT '13 . O. Kotaba, J. Nowotsch, M. Paulitsch, S. Petters, and H. Theiling. Multicore in real-time systems - temporal isolation challenges due to shared resources. In WICERT '13."},{"key":"e_1_3_2_1_28_1","volume-title":"ECRTS '14","author":"Krishnapillai Y.","unstructured":"Y. Krishnapillai , Z. Wu , and R. Pellizzoni . ROC: A rank-switching, open-row DRAM controller for time-predictable systems . In ECRTS '14 . Y. Krishnapillai, Z. Wu, and R. Pellizzoni. ROC: A rank-switching, open-row DRAM controller for time-predictable systems. In ECRTS '14."},{"key":"e_1_3_2_1_29_1","unstructured":"LITMUSRT Project. http:\/\/www.litmus-rt.org\/.  LITMUS RT Project. http:\/\/www.litmus-rt.org\/."},{"key":"e_1_3_2_1_30_1","volume-title":"ICESS '10","author":"Mollison M.","unstructured":"M. Mollison , J. Erickson , J. Anderson , S. Baruah , and J. Scoredos . Mixed criticality real-time scheduling for multicore systems . In ICESS '10 . M. Mollison, J. Erickson, J. Anderson, S. Baruah, and J. Scoredos. Mixed criticality real-time scheduling for multicore systems. In ICESS '10."},{"key":"e_1_3_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1109\/ECRTS.2014.20"},{"key":"e_1_3_2_1_32_1","volume-title":"DATE '10","author":"Pellizzoni R.","unstructured":"R. Pellizzoni , A. Schranzhofer , J. Chen , M. Caccamo , and L. Thiele . Worst case delay analysis for memory interference in multicore systems . In DATE '10 . R. Pellizzoni, A. Schranzhofer, J. Chen, M. Caccamo, and L. Thiele. Worst case delay analysis for memory interference in multicore systems. In DATE '10."},{"key":"e_1_3_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1023\/B:TIME.0000016129.97430.c6"},{"key":"e_1_3_2_1_34_1","volume-title":"RTAS '16","author":"Tabish R.","unstructured":"R. Tabish , R. Mancuso , S. Wasly , A. Alhammad , S. Phatak , R. Pellizzoni , and M. Caccamo . A real-time scratchpad-centric OS for multi-core embedded systems . In RTAS '16 . R. Tabish, R. Mancuso, S. Wasly, A. Alhammad, S. Phatak, R. Pellizzoni, and M. Caccamo. A real-time scratchpad-centric OS for multi-core embedded systems. In RTAS '16."},{"key":"e_1_3_2_1_35_1","volume-title":"RTAS '16","author":"Valsan P.","unstructured":"P. Valsan , H. Yun , and F. Farshchi . Taming non-blocking caches to improve isolation in multicore real-time systems . In RTAS '16 . P. Valsan, H. Yun, and F. Farshchi. Taming non-blocking caches to improve isolation in multicore real-time systems. In RTAS '16."},{"key":"e_1_3_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1109\/RTSS.2007.35"},{"key":"e_1_3_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1109\/ECRTS.2013.26"},{"key":"e_1_3_2_1_38_1","volume-title":"RTAS '16","author":"Xu M.","unstructured":"M. Xu , L. T. X. Phan , H. Y. Choi , and I. Lee . Analysis and implementation of global preemptive fixed-priority scheduling with dynamic cache allocation . In RTAS '16 . M. Xu, L. T. X. Phan, H. Y. Choi, and I. Lee. Analysis and implementation of global preemptive fixed-priority scheduling with dynamic cache allocation. In RTAS '16."},{"key":"e_1_3_2_1_39_1","volume-title":"RTAS '17","author":"Xu M.","unstructured":"M. Xu , L. T. X. Phan , H. Y. Choi , and I. Lee . vCAT: Dynamic cache management using CAT virtualization . In RTAS '17 . M. Xu, L. T. X. Phan, H. Y. Choi, and I. Lee. vCAT: Dynamic cache management using CAT virtualization. In RTAS '17."},{"key":"e_1_3_2_1_40_1","volume-title":"RTAS '14","author":"Yun H.","unstructured":"H. Yun , R. Mancuso , Z. Wu , and R. Pellizzoni . PALLOC: DRAM bank-aware memory allocator for performance isolation on multicoore platforms . In RTAS '14 . H. Yun, R. Mancuso, Z. Wu, and R. Pellizzoni. PALLOC: DRAM bank-aware memory allocator for performance isolation on multicoore platforms. In RTAS '14."},{"key":"e_1_3_2_1_41_1","doi-asserted-by":"publisher","DOI":"10.1109\/ECRTS.2012.32"}],"event":{"name":"RTNS '17: 25th International Conference on Real-Time Networks and Systems","location":"Grenoble France","acronym":"RTNS '17"},"container-title":["Proceedings of the 25th International Conference on Real-Time Networks and Systems"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3139258.3139268","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3139258.3139268","content-type":"application\/pdf","content-version":"vor","intended-application":"syndication"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3139258.3139268","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T02:11:17Z","timestamp":1750212677000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3139258.3139268"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,10,4]]},"references-count":41,"alternative-id":["10.1145\/3139258.3139268","10.1145\/3139258"],"URL":"https:\/\/doi.org\/10.1145\/3139258.3139268","relation":{},"subject":[],"published":{"date-parts":[[2017,10,4]]},"assertion":[{"value":"2017-10-04","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}