{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,22]],"date-time":"2026-03-22T09:29:07Z","timestamp":1774171747136,"version":"3.50.1"},"publisher-location":"New York, NY, USA","reference-count":26,"publisher":"ACM","license":[{"start":{"date-parts":[[2017,10,4]],"date-time":"2017-10-04T00:00:00Z","timestamp":1507075200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"European Union","award":["688860"],"award-info":[{"award-number":["688860"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2017,10,4]]},"DOI":"10.1145\/3139258.3139270","type":"proceedings-article","created":{"date-parts":[[2017,11,8]],"date-time":"2017-11-08T13:20:39Z","timestamp":1510147239000},"page":"48-57","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":24,"title":["SiGAMMA"],"prefix":"10.1145","author":[{"given":"Nicola","family":"Capodieci","sequence":"first","affiliation":[{"name":"University of Modena and Reggio Emilia, Modena, Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Roberto","family":"Cavicchioli","sequence":"additional","affiliation":[{"name":"University of Modena and Reggio Emilia, Modena, Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Paolo","family":"Valente","sequence":"additional","affiliation":[{"name":"University of Modena and Reggio Emilia, Modena, Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Marko","family":"Bertogna","sequence":"additional","affiliation":[{"name":"University of Modena and Reggio Emilia, Modena, Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2017,10,4]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"2014. NVIDIA TK1 Development kit. http:\/\/www.nvidia.com\/object\/jetson-tk1--embedded-dev-kit.html. (2014).  2014. NVIDIA TK1 Development kit. http:\/\/www.nvidia.com\/object\/jetson-tk1--embedded-dev-kit.html. (2014)."},{"key":"e_1_3_2_1_2_1","unstructured":"2015. NVIDIA TX1 Development kit. http:\/\/www.nvidia.com\/object\/jetson-tx1--dev-kit.html. (2015).  2015. NVIDIA TX1 Development kit. http:\/\/www.nvidia.com\/object\/jetson-tx1--dev-kit.html. (2015)."},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/RTCSA.2012.48"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/ECRTS.2012.15"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/2063384.2063400"},{"key":"e_1_3_2_1_6_1","volume-title":"European Conference on Parallel Processing. Springer, 373--380","author":"Breitbart Jens","year":"2010","unstructured":"Jens Breitbart . 2010 . Static GPU threads and an improved scan algorithm . In European Conference on Parallel Processing. Springer, 373--380 . Jens Breitbart. 2010. Static GPU threads and an improved scan algorithm. In European Conference on Parallel Processing. Springer, 373--380."},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/PAAP.2015.13"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/ETFA.2017.8247615"},{"key":"e_1_3_2_1_9_1","unstructured":"G. Durrieu M. Faug\u00c3\u013are S. Girbal D. Gracia P\u00c3l'rez C. Pagetti and W. Puffitsch. 2014. Predictable Flight Management System implementation on a Multicore processor. In Embedded Real Time Software (ERTS'14). TOULOUSE France.  G. Durrieu M. Faug\u00c3\u013are S. Girbal D. Gracia P\u00c3l'rez C. Pagetti and W. Puffitsch. 2014. Predictable Flight Management System implementation on a Multicore processor. In Embedded Real Time Software (ERTS'14). TOULOUSE France."},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/RTSS.2013.12"},{"key":"e_1_3_2_1_11_1","volume-title":"Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 318--321","author":"Forsberg Bj\u00f6rn","year":"2017","unstructured":"Bj\u00f6rn Forsberg , Andrea Marongiu , and Luca Benini . 2017 . GPUguard: Towards supporting a predictable execution model for heterogeneous SoC. In 2017 Design , Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 318--321 . Bj\u00f6rn Forsberg, Andrea Marongiu, and Luca Benini. 2017. GPUguard: Towards supporting a predictable execution model for heterogeneous SoC. In 2017 Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 318--321."},{"key":"e_1_3_2_1_12_1","volume-title":"Innovative Parallel Computing (InPar)","author":"Gupta Kshitij","year":"2012","unstructured":"Kshitij Gupta , Jeff A Stuart , and John D Owens . 2012. A study of persistent threads style GPU programming for GPGPU workloads . In Innovative Parallel Computing (InPar) , 2012 . IEEE , 1--14. Kshitij Gupta, Jeff A Stuart, and John D Owens. 2012. A study of persistent threads style GPU programming for GPGPU workloads. In Innovative Parallel Computing (InPar), 2012. IEEE, 1--14."},{"key":"e_1_3_2_1_13_1","volume-title":"WATERS Industrial Challenge","author":"Hamann Arne","year":"2017","unstructured":"Arne Hamann , Dakshina Dasari , Simon Kramer , Michael Pressler , FalkWurst, and Dirk Ziegenbein . 2017. WATERS Industrial Challenge 2017 . http:\/\/ecrts.eit.uni-kl.de\/forum\/download\/file.php?id=60&sid=fdaf5540bb967f3f923d96bc74ea2f7a. (2017). Arne Hamann, Dakshina Dasari, Simon Kramer, Michael Pressler, FalkWurst, and Dirk Ziegenbein. 2017. WATERS Industrial Challenge 2017. http:\/\/ecrts.eit.uni-kl.de\/forum\/download\/file.php?id=60&sid=fdaf5540bb967f3f923d96bc74ea2f7a. (2017)."},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.5555\/2120959.2121120"},{"key":"e_1_3_2_1_15_1","unstructured":"Shinpei Kato Karthik Lakshmanan Raj Rajkumar and Yutaka Ishikawa. 2011. TimeGraph: GPU scheduling for real-time multi-tasking environments.  Shinpei Kato Karthik Lakshmanan Raj Rajkumar and Yutaka Ishikawa. 2011. TimeGraph: GPU scheduling for real-time multi-tasking environments."},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2015.2463813"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/RTAS.2011.33"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.5555\/2485288.2485400"},{"key":"e_1_3_2_1_19_1","first-page":"223","article-title":"Unified memory systems and methods. (Jan. 20 2015)","volume":"14","author":"Rao Amit","year":"2015","unstructured":"Amit Rao , Ashish Srivastava , KINI Yogesh , Alban Douillet , Geoffrey Gerfin , Mayank Kaushik , Nikita Shulga , Vyas Venkataraman , David Fontaine , Mark Hairgrove , 2015 . Unified memory systems and methods. (Jan. 20 2015) . US Patent App. 14\/601 , 223 . Amit Rao, Ashish Srivastava, KINI Yogesh, Alban Douillet, Geoffrey Gerfin, Mayank Kaushik, Nikita Shulga, Vyas Venkataraman, David Fontaine, Mark Hairgrove, et al. 2015. Unified memory systems and methods. (Jan. 20 2015). US Patent App. 14\/601,223.","journal-title":"US Patent App."},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/SIES.2016.7509411"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.5555\/2775334.2775336"},{"key":"e_1_3_2_1_22_1","volume-title":"2013 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS). 215--224","author":"Weaver V. M.","unstructured":"V. M. Weaver , D. Terpstra , and S. Moore . 2013. Non-determinism and overcount on modern hardware performance counter implementations . In 2013 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS). 215--224 . V. M. Weaver, D. Terpstra, and S. Moore. 2013. Non-determinism and overcount on modern hardware performance counter implementations. In 2013 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS). 215--224."},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2010.5470477"},{"key":"e_1_3_2_1_24_1","volume-title":"Protecting memory-performance critical sections in soft real-time applications. arXiv preprint arXiv:1502.02287","author":"Yun Heechul","year":"2015","unstructured":"Heechul Yun , Santosh Gondi , and Siddhartha Biswas . 2015. Protecting memory-performance critical sections in soft real-time applications. arXiv preprint arXiv:1502.02287 ( 2015 ). Heechul Yun, Santosh Gondi, and Siddhartha Biswas. 2015. Protecting memory-performance critical sections in soft real-time applications. arXiv preprint arXiv:1502.02287 (2015)."},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1109\/RTAS.2013.6531079"},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2013.257"}],"event":{"name":"RTNS '17: 25th International Conference on Real-Time Networks and Systems","location":"Grenoble France","acronym":"RTNS '17"},"container-title":["Proceedings of the 25th International Conference on Real-Time Networks and Systems"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3139258.3139270","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3139258.3139270","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T02:11:17Z","timestamp":1750212677000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3139258.3139270"}},"subtitle":["server based integrated GPU arbitration mechanism for memory accesses"],"short-title":[],"issued":{"date-parts":[[2017,10,4]]},"references-count":26,"alternative-id":["10.1145\/3139258.3139270","10.1145\/3139258"],"URL":"https:\/\/doi.org\/10.1145\/3139258.3139270","relation":{},"subject":[],"published":{"date-parts":[[2017,10,4]]},"assertion":[{"value":"2017-10-04","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}