{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T04:36:11Z","timestamp":1750221371085,"version":"3.41.0"},"reference-count":18,"publisher":"Association for Computing Machinery (ACM)","issue":"4","license":[{"start":{"date-parts":[[2017,12,5]],"date-time":"2017-12-05T00:00:00Z","timestamp":1512432000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/501100004359","name":"Vetenskapsr\u00e5det","doi-asserted-by":"publisher","award":["2012-4924"],"award-info":[{"award-number":["2012-4924"]}],"id":[{"id":"10.13039\/501100004359","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Archit. Code Optim."],"published-print":{"date-parts":[[2017,12,31]]},"abstract":"<jats:p>Most systems allocate computational resources to each executing task without any actual knowledge of the application\u2019s Quality-of-Service (QoS) requirements. Such best-effort policies lead to overprovisioning of the resources and increase energy loss. This work assumes applications with soft QoS requirements and exploits the inherent timing slack to minimize the allocated computational resources to reduce energy consumption.<\/jats:p>\n          <jats:p>We propose a lightweight progress-tracking methodology based on the outer loops of application kernels. It builds on online history and uses it to estimate the total execution time. The prediction of the execution time and the QoS requirements are then used to schedule the application on a heterogeneous architecture with big out-of-order cores and small (LITTLE) in-order cores and select the minimum operating frequency, using DVFS, that meets the deadline. Our scheme is effective in exploiting the timing slack of each application. We show that it can reduce the energy consumption by more than 20% without missing any computational deadlines.<\/jats:p>","DOI":"10.1145\/3148053","type":"journal-article","created":{"date-parts":[[2017,12,6]],"date-time":"2017-12-06T21:23:15Z","timestamp":1512595395000},"page":"1-25","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":9,"title":["SLOOP"],"prefix":"10.1145","volume":"14","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-0477-4540","authenticated-orcid":false,"given":"M. Waqar","family":"Azhar","sequence":"first","affiliation":[{"name":"Chalmers University of Technology, Gothenburg, Sweden"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Per","family":"Stenstr\u00f6m","sequence":"additional","affiliation":[{"name":"Chalmers University of Technology, Gothenburg, Sweden"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Vassilis","family":"Papaefstathiou","sequence":"additional","affiliation":[{"name":"Chalmers University of Technology, Gothenburg, Sweden"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2017,12,5]]},"reference":[{"volume-title":"Proceedings of the 2012 39th Annual International Symposium on Computer Architecture (ISCA\u201912)","author":"Van Craeynest K.","key":"e_1_2_2_1_1"},{"key":"e_1_2_2_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/1186736.1186737"},{"key":"e_1_2_2_3_1","unstructured":"H.-D. Cho H. Chung and M. Kang. 2013. Heterogeneous Multi-Processing Solution of Exynos 5 Octa with ARM big.LITTLETM Technology. Retrieved from https:\/\/www.arm.com\/files\/pdf\/Heterogeneous_Multi_Processing_Solution_of_Exynos_5_Octa_with_ARM_bigLITTLE_Technology.pdf.  H.-D. Cho H. Chung and M. Kang. 2013. Heterogeneous Multi-Processing Solution of Exynos 5 Octa with ARM big.LITTLETM Technology. Retrieved from https:\/\/www.arm.com\/files\/pdf\/Heterogeneous_Multi_Processing_Solution_of_Exynos_5_Octa_with_ARM_bigLITTLE_Technology.pdf."},{"key":"e_1_2_2_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/379240.379270"},{"volume-title":"Proceedings of the 34th Annual ACM\/IEEE International Symposium on Microarchitecture (MICRO-34)","author":"Hughes C. J.","key":"e_1_2_2_5_1"},{"key":"e_1_2_2_6_1","doi-asserted-by":"crossref","unstructured":"S. Kaxiras and M. Martonosi. 2008. Computer Architecture Techniques for Power-Efficiency. Morgan and Claypool Publishers.   S. Kaxiras and M. Martonosi. 2008. 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Morgan and Claypool Publishers.","DOI":"10.1007\/978-3-031-01721-6"},{"volume-title":"Proceedings of the Conference on Design, Automation & Test in Europe (DATE\u201914)","author":"Kim M.","key":"e_1_2_2_7_1"},{"key":"e_1_2_2_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/CIT.2010.317"},{"volume-title":"Proceedings of the 36th Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO-36)","author":"Kumar R.","key":"e_1_2_2_9_1"},{"volume-title":"Proceedings of the 2005 IEEE International Workload Characterization Symposium. 34--45","author":"Li M.-L.","key":"e_1_2_2_10_1"},{"key":"e_1_2_2_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSAC.2007.070509"},{"key":"e_1_2_2_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2012.6169031"},{"key":"e_1_2_2_13_1","doi-asserted-by":"publisher","DOI":"10.5120\/21034-3106"},{"volume-title":"Proceedings of the HiPEAC Workshop on Energy Efficiency with Heterogeneous Computing.","author":"Lilius J.","key":"e_1_2_2_14_1"},{"key":"e_1_2_2_15_1","doi-asserted-by":"crossref","unstructured":"M. Sj\u00e4lander M. Martonosi and S. Kaxiras. 2014. Power-Efficient Computer Architectures: Recent Advances. Morgan and Claypool Publishers.  M. Sj\u00e4lander M. Martonosi and S. Kaxiras. 2014. Power-Efficient Computer Architectures: Recent Advances. Morgan and Claypool Publishers.","DOI":"10.1007\/978-3-031-01745-2"},{"key":"e_1_2_2_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2012.6189203"},{"key":"e_1_2_2_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2014.17"},{"key":"e_1_2_2_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/2714575"}],"container-title":["ACM Transactions on Architecture and Code Optimization"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3148053","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3148053","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T02:26:33Z","timestamp":1750213593000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3148053"}},"subtitle":["QoS-Supervised Loop Execution to Reduce Energy on Heterogeneous Architectures"],"short-title":[],"issued":{"date-parts":[[2017,12,5]]},"references-count":18,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2017,12,31]]}},"alternative-id":["10.1145\/3148053"],"URL":"https:\/\/doi.org\/10.1145\/3148053","relation":{},"ISSN":["1544-3566","1544-3973"],"issn-type":[{"type":"print","value":"1544-3566"},{"type":"electronic","value":"1544-3973"}],"subject":[],"published":{"date-parts":[[2017,12,5]]},"assertion":[{"value":"2017-02-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2017-09-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2017-12-05","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}